Patents by Inventor Tetsuya Hiraoka
Tetsuya Hiraoka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8653381Abstract: A wiring board includes: a first wiring; a second wiring being disposed adjacently to the first wiring; a third wiring being disposed adjacently to the first wiring; a fourth wiring being disposed adjacently to the third wiring; and an insulating layer, wherein the second wiring and the fourth wiring are disposed adjacently to each other, the first wiring and the fourth wiring are not overlapped, the second wiring and the third wiring are not overlapped, a crest and a trough are provided on a side face of the first wiring, the crest and the trough are provided on a side face of the second wiring, the trough provided on the side face of the first wiring and the third wiring are overlapped, and the trough provided on the side face of the second wiring and the fourth wiring are overlapped.Type: GrantFiled: December 16, 2011Date of Patent: February 18, 2014Assignee: Fujitsu Semiconductor LimitedInventor: Tetsuya Hiraoka
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Publication number: 20120241197Abstract: A wiring board includes: a first wiring; a second wiring being disposed adjacently to the first wiring; a third wiring being disposed adjacently to the first wiring; a fourth wiring being disposed adjacently to the third wiring; and an insulating layer, wherein the second wiring and the fourth wiring are disposed adjacently to each other, the first wiring and the fourth wiring are not overlapped, the second wiring and the third wiring are not overlapped, a crest and a trough are provided on a side face of the first wiring, the crest and the trough are provided on a side face of the second wiring, the trough provided on the side face of the first wiring and the third wiring are overlapped, and the trough provided on the side face of the second wiring and the fourth wiring are overlapped.Type: ApplicationFiled: December 16, 2011Publication date: September 27, 2012Applicant: FUJITSU SEMICONDUCTOR LIMITEDInventor: Tetsuya HIRAOKA
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Patent number: 8048719Abstract: A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.Type: GrantFiled: April 6, 2009Date of Patent: November 1, 2011Assignee: Fujitsu Semiconductor LimitedInventors: Takao Nishimura, Tetsuya Hiraoka
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Publication number: 20090191702Abstract: A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.Type: ApplicationFiled: April 6, 2009Publication date: July 30, 2009Applicant: FUJITSU LIMITEDInventors: Takao NISHIMURA, Tetsuya Hiraoka
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Patent number: 7528460Abstract: A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.Type: GrantFiled: May 1, 2006Date of Patent: May 5, 2009Assignee: Fujitsu Microelectronics LimitedInventors: Takao Nishimura, Tetsuya Hiraoka
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Publication number: 20070170600Abstract: A semiconductor device capable of preventing contact between electrode terminals and a die pad as well as capable of surely performing wire bonding to the electrode terminals. A passive component is formed such that a vertical height of each electrode terminal is higher than that of an element part. More specifically, each cross-sectional area of the electrode terminals is slightly larger than that of the element part. Therefore, an upper part and lower part of each electrode terminal are slightly higher than (project from) the element part. Through an adhesive, the passive component is fixed such that the element part is located on the high position part so as to be nearly parallel to a substrate surface. Further, a part of each electrode terminal (bottom part) is located in each space within concave parts. Thus, a predetermined space is formed between each of the electrode terminals and the die pad.Type: ApplicationFiled: May 1, 2006Publication date: July 26, 2007Applicant: FUJITSU LIMITEDInventors: Takao Nishimura, Tetsuya Hiraoka
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Patent number: 7138723Abstract: A semiconductor chip is secured in a state deformed into a substantially cylinder shape by a coating material formed on its surface. The deformed semiconductor chip is flip-chip connected to an interposer and sealed with sealing resin onto the interposer. Solder balls are provided, as external terminals, on the other side of the interposer.Type: GrantFiled: December 8, 2004Date of Patent: November 21, 2006Assignee: Fujitsu LimitedInventors: Kazuyuki Aiba, Akira Takashima, Kaname Ozawa, Tetsuya Hiraoka, Takaaki Suzuki, Yasurou Matsuzaki
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Publication number: 20060226529Abstract: The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.Type: ApplicationFiled: June 8, 2006Publication date: October 12, 2006Applicant: FUJITSU LIMITEDInventors: Yoshiharu Kato, Satoru Kawamoto, Fumihiko Taniguchi, Tetsuya Hiraoka, Akira Takashima
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Patent number: 6972487Abstract: The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor Substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second Semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.Type: GrantFiled: January 25, 2002Date of Patent: December 6, 2005Assignee: Fujitsu LimitedInventors: Yoshiharu Kato, Satoru Kawamoto, Fumihiko Taniguchi, Tetsuya Hiraoka, Akira Takashima
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Publication number: 20050161794Abstract: The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.Type: ApplicationFiled: March 16, 2005Publication date: July 28, 2005Applicant: Fujitsu LimitedInventors: Yoshiharu Kato, Satoru Kawamoto, Fumihiko Taniguchi, Tetsuya Hiraoka, Akira Takashima
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Publication number: 20050082684Abstract: A semiconductor chip is secured in a state deformed into a substantially cylinder shape by a coating material formed on its surface. The deformed semiconductor chip is flip-chip connected to an interposer and sealed with sealing resin onto the interposer. Solder balls are provided, as external terminals, on the other side of the interposer.Type: ApplicationFiled: December 8, 2004Publication date: April 21, 2005Applicant: FUJITSU LIMITEDInventors: Kazuyuki Aiba, Akira Takashima, Kaname Ozawa, Tetsuya Hiraoka, Takaaki Suzuki, Yasurou Matsuzaki
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Patent number: 6740970Abstract: A semiconductor device is configured of a first semiconductor chip mounted on a substrate, a plate member arranged on the first semiconductor chip, and a second semiconductor chip arranged on the plate member. Bonding wires electrically connect the pads of the first semiconductor chip and the pads of the second semiconductor chip to the pads of the substrate, and a sealing resin seals the first semiconductor chip and the second semiconductor chip. A first portion of the plate member is displaced away from the ends of the first and second semiconductor chips, and a second portion of the plate member extending perpendicular to the first portion, projects outward from the first and second semiconductor chips to be exposed to the outside.Type: GrantFiled: October 10, 2001Date of Patent: May 25, 2004Assignee: Fujitsu LimitedInventors: Tetsuya Hiraoka, Akira Takashima
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Patent number: 6580173Abstract: A substrate of a semiconductor device has a first surface on which a semiconductor element is fixed and a second surface opposite to the first surface. An adhesive is provided between the semiconductor element and the first surface of the substrate. At least one though hole is formed which extends between the first surface and the second surface of the substrate. A pattern member is formed on the first surface of the substrate so as to cover a part of an opening of the through hole.Type: GrantFiled: December 4, 2000Date of Patent: June 17, 2003Assignee: Fujitsu LimitedInventors: Akira Okada, Tetsuya Hiraoka, Kazuyuki Aiba
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Publication number: 20020171136Abstract: A semiconductor device is configured of a first semiconductor chip mounted on a substrate, a plate member arranged on the first semiconductor chip, and a second semiconductor chip arranged on the plate member. Bonding wires electrically connect the pads of the first semiconductor chip and the pads of the second semiconductor chip to the pads of the substrate, and a sealing resin seals the first semiconductor chip and the second semiconductor chip. A first portion of the plate member is displaced away from the ends of the first and second semiconductor chips, and a second portion of the plate member extending perpendicular to the first portion, projects outward from the first and second semiconductor chips to be exposed to the outside.Type: ApplicationFiled: October 10, 2001Publication date: November 21, 2002Applicant: Fujitsu LimitedInventors: Tetsuya Hiraoka, Akira Takashima
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Publication number: 20020140107Abstract: The present invention relates to a semiconductor device having an MCP (Multi Chip Package) structure in which a plurality of semiconductor chips are mounted in the same package, a manufacturing method therefor and a semiconductor substrate used therein. Atop a first semiconductor chip that is a memory chip is mounted a second semiconductor chip that is a logic chip, with a first functional chip and a second functional chip that together form the first semiconductor chip being joined together via an unsliced scribe line. Additionally, a first functional chip and a second functional chip are given the same chip composition (32-bit memory) and respectively rotated 180 degrees relative to each other. These configurations are intended to improve performance, reduce costs and improve yield.Type: ApplicationFiled: January 31, 2002Publication date: October 3, 2002Applicant: Fujitsu LimitedInventors: Yoshiharu Kato, Satoru Kawamoto, Fumihiko Taniguchi, Tetsuya Hiraoka, Akira Takashima
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Patent number: 6459161Abstract: The semiconductor device of the present invention with an IC chip provided on one side of a substrate, comprises a plurality of connection terminals, which are provided on the other side of the substrate, are electrically connected to the IC chip through electrical connecting devices, form a rectangular grid array, and are arranged in positions other than corners of the array.Type: GrantFiled: November 9, 1999Date of Patent: October 1, 2002Assignees: NEC Corporation, Fujitsu Limited, Kabushiki Kaisha ToshibaInventors: Masayoshi Hirata, Yasuhiro Suzuki, Tetsuya Hiraoka, Mitsutaka Sato
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Publication number: 20020105096Abstract: The semiconductor device of the present invention with an IC chip provided on one side of a substrate, comprises a plurality of connection terminals, which are provided on the other side of the substrate, are electrically connected to the IC chip through electrical connecting devices, form a rectangular grid array, and are arranged in positions other than corners of the array.Type: ApplicationFiled: November 9, 1999Publication date: August 8, 2002Inventors: MASAYOSHI HIRATA, YASUHIRO SUZUKI, TETSUYA HIRAOKA, MITSUTAKA SATO
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Publication number: 20010042908Abstract: A substrate of a semiconductor device has a first surface on which a semiconductor element is fixed and a second surface opposite to the first surface. An adhesive is provided between the semiconductor element and the first surface of the substrate. At least one though hole is formed which extends between the first surface and the second surface of the substrate. A pattern member is formed on the first surface of the substrate so as to cover a part of an opening of the through hole.Type: ApplicationFiled: December 4, 2000Publication date: November 22, 2001Inventors: Akira Okada, Tetsuya Hiraoka, Kazuyuki Aiba
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Patent number: 6316838Abstract: A semiconductor device includes a substrate provided with a plurality of leads, a face-down semiconductor element provided on one surface of the substrate, a first stacked semiconductor element and a second stacked semiconductor element provided on another surface of the substrate and connected to the substrate by wires, and an extended wiring mechanism for connecting electrodes of the face-down semiconductor element and electrodes of the first and second semiconductor elements. The connected electrodes are equi-electrodes whose electrical characteristics are equal.Type: GrantFiled: March 20, 2000Date of Patent: November 13, 2001Assignee: Fujitsu LimitedInventors: Kaname Ozawa, Hayato Okuda, Tetsuya Hiraoka, Mitsutaka Sato, Yuji Akashi, Akira Okada, Masahiko Harayama
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Patent number: 5566545Abstract: An exhaust gas-treating process by capturing particulates in exhaust gas discharged from an internal combustion engine with use of a honeycomb structural filter, the process including the steps of: (1) capturing the particulates contained in the exhaust gas by passing the exhaust gas through the filter; (2) stopping flow of the exhaust gas through the filter and transferring the captured particulates to a location remote from and outside an exhaust line by flowing the particulates captured by the filter in a direction reverse to a flowing direction of the exhaust gas; and (3) burning the particulates and discharging a burnt matter outside. The filter preferably has a honeycomb structural body and second sealed portions in first and second rows at opposite ends of the honeycomb structural body, respectively.Type: GrantFiled: August 10, 1994Date of Patent: October 22, 1996Assignee: NGK Insulators, Ltd.Inventors: Toshihiko Hijikata, Tetsuya Hiraoka, Kazuhiko Umehara