Abstract: An address region of an internal bus wherein a burst access can be utilized in an external bus is set in an address table. A DMA control unit determines whether or not a burst access can be utilized in the external bus by comparing an address in an access to the internal bus with an address region set in the address table. Then, the DMA control unit carries out a direct memory access transfer by utilizing a burst access when it is determined that the burst access can be utilized in the external bus. Accordingly, the DMA control unit can carry out a DMA transfer by using a burst access without the intervention of a FIFO memory and it becomes possible to carry out a high speed DMA transfer.

Abstract: A DMA controller includes: a bus availability frequency register setting a ratio of a bus access frequency of DMA transfer to a bus access frequency of another bus master; a DMA request detecting portion detecting a DMA request; a bus availability counter counting the bus access frequency in accordance with the ratio set in the bus availability frequency counter; a bus access request controlling portion controlling the bus access request based on the DMA request detected by the DMA request detecting portion and the counted result of the counter; and a DMA controlling portion controlling execution of DMA transfer. Thus, a band which allows another bus master to use a bus during DMA transfer can be predicted.

Abstract: An address region of an internal bus wherein a burst access can be utilized in an external bus is set in an address table. A DMA control unit determines whether or not a burst access can be utilized in the external bus by comparing an address in an access to the internal bus with an address region set in the address table. Then, the DMA control unit carries out a direct memory access transfer by utilizing a burst access when it is determined that the burst access can be utilized in the external bus. Accordingly, the DMA control unit can carry out a DMA transfer by using a burst access without the intervention of a FIFO memory and it becomes possible to carry out a high speed DMA transfer.

Abstract: A Positioning device includes a downconversion unit receiving positioning signals from satellites and converting the signals to an intermediate-frequency signal, and carrier search units using an output from the downconversion unit to search for a carrier wave of the received signals. The carrier search unit separates the received signal into in-phase and quadrate channel signals and spectrum-despreads them and then applies real Fast Fourier Transform to them. Of each frequency component, a signal corresponding to 0 Hz is corrected with a sum of all quadrate channel components to obtain a frequency difference between a local carrier and the carrier wave.

Abstract: A DMA controller includes: a bus availability frequency register setting a ratio of a bus access frequency of DMA transfer to a bus access frequency of another bus master; a DMA request detecting portion detecting a DMA request; a bus availability counter counting the bus access frequency in accordance with the ratio set in the bus availability frequency counter; a bus access request controlling portion controlling the bus access request based on the DMA request detected by the DMA request detecting portion and the counted result of the counter; and a DMA controlling portion controlling execution of DMA transfer. Thus, a band which allows another bus master to use a bus during DMA transfer can be predicted.

Abstract: When cells inputted from an incoming line (30) are demultiplexed cells for transmitting voice signals, a demultiplexer (31) extracts the signals from the cells and distributes the same to lines (33.sub.1 to 33.sub.n) corresponding to virtual channel identifiers of the cells, while distributing other cells to a line (33.sub.0) as such in other case. A multiplexed cell generator (35) reads a plurality of signals passing through FIFOs (34.sub.1 to 34.sub.n) in a cycle of 125 .mu.sec., and stores the same in an information field of a multiplexed cell. A demultiplexer (39) preferentially outputs the cell of the line (33.sub.0) to an outgoing line (310), while inserting a multiplexed cell passing through an FIFO (38) in a vacant cell caused in the line (33.sub.0) and outputting the same to the outgoing line (310). Thus, voice signals of a plurality of virtual channels are multiplexed in a transmission path on the outgoing line side, whereby waste of the band is reduced.