Patents by Inventor Tetsuya Kai
Tetsuya Kai has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20170040340Abstract: According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and charge storage film. The stacked body includes the plurality of electrode layers separately stacked each other. The semiconductor body is provided in the stacked body and extends in a stack direction of the stacked body and includes an oxide semiconductor. The charge storage film is provided between the semiconductor body and the plurality of electrode layers.Type: ApplicationFiled: October 20, 2016Publication date: February 9, 2017Inventors: Katsuaki NATORI, Masayuki TANAKA, Keiichi SAWA, Tetsuya KAI, Shinji MORI
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Patent number: 9293563Abstract: According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.Type: GrantFiled: June 25, 2014Date of Patent: March 22, 2016Assignee: KABUSHIKI KAISHA TOSHIBAInventors: Tetsuya Kai, Yoshio Ozawa, Ryota Fujitsuka, Yoshitaka Tsunashima
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Publication number: 20160079262Abstract: According to one embodiment, a semiconductor memory device includes a conductive layer; a stacked body provided on the conductive layer and including a plurality of electrode layers separately stacked each other; a semiconductor body provided in the stacked body and extending in a stacking direction in the stacking body and including a lower end portion provided in the conductive layer; and a charge storage film provided between the semiconductor body and the plurality of electrode layers. As viewed in the stacking direction, a maximum width of the lower end portion is larger than a maximum width of the semiconductor body provided inside a bottom surface of the charge storage film.Type: ApplicationFiled: February 26, 2015Publication date: March 17, 2016Inventors: Shinji Mori, Yoshio Ozawa, Tetsuya Kai
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Publication number: 20160064406Abstract: According to one embodiment, a semiconductor memory device includes a stacked body; a semiconductor body; and charge storage film. The stacked body includes the plurality of electrode layers separately stacked each other. The semiconductor body is provided in the stacked body and extends in a stack direction of the stacked body and includes an oxide semiconductor. The charge storage film is provided between the semiconductor body and the plurality of electrode layers.Type: ApplicationFiled: February 4, 2015Publication date: March 3, 2016Inventors: Katsuaki NATORI, Masayuki Tanaka, Keiichi Sawa, Tetsuya Kai, Shinji Mori
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Publication number: 20140308789Abstract: According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.Type: ApplicationFiled: June 25, 2014Publication date: October 16, 2014Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tetsuya Kai, Yoshio Ozawa, Ryota Fujitsuka, Yoshitaka Tsunashima
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Patent number: 8829593Abstract: A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.Type: GrantFiled: March 18, 2010Date of Patent: September 9, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Katsuyuki Sekine, Kensuke Takano, Masaaki Higuchi, Tetsuya Kai, Yoshio Ozawa
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Patent number: 8803221Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate; a tunnel insulating film on the substrate; a charge storage layer on the tunnel insulating film; a block insulating film on the charge storage layer; a first element isolation insulating film in an element isolation trench in the substrate, having a bottom surface lower than an interface between the substrate and the tunnel insulating film, and having a top surface lower than an interface between the charge storage layer and the block insulating film; a second element isolation insulating film on the first element isolation insulating film, protruding to a top surface of the block insulating film, in contact with a side surface of the block insulating film, and having a higher Si concentration than the block insulating film; and a control gate electrode on the block insulating film and on the second element isolation insulating film.Type: GrantFiled: September 13, 2011Date of Patent: August 12, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kai, Yoshio Ozawa
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Patent number: 8796757Abstract: According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.Type: GrantFiled: March 21, 2011Date of Patent: August 5, 2014Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kai, Yoshio Ozawa, Ryota Fujitsuka, Yoshitaka Tsunashima
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Publication number: 20130256780Abstract: A semiconductor device comprising: a semiconductor substrate; a tunnel insulating film provided on the semiconductor substrate; a charge accumulation film having a rough interface in the charge accumulation film provided on the tunnel insulating film; a block insulating film provided on the charge accumulation film; and a gate electrode provided on the block insulating film.Type: ApplicationFiled: March 11, 2013Publication date: October 3, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Tetsuya KAI, Masayuki TANAKA
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Publication number: 20130256779Abstract: A method of manufacturing a semiconductor device comprising: forming a first insulating film on a semiconductor substrate; forming an adsorption film on the first insulating film; forming a first film containing germanium on the adsorption film; forming a second insulating film on the first film; forming a floating electrode film on the second insulating film; forming a third insulating film on the floating electrode film; and forming a gate electrode on the third insulating film.Type: ApplicationFiled: March 14, 2013Publication date: October 3, 2013Applicant: Kabushiki Kaisha ToshibaInventors: Keiichi SAWA, Tetsuya Kai, Shinji Mori, Kenichiro Toratani, Masayuki Tanaka
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Patent number: 8254175Abstract: A semiconductor device includes a semiconductor region, a tunnel insulating film formed on the semiconductor region, a charge-storage insulating film formed on the tunnel insulating film, a block insulating film formed on the charge-storage insulating film, and a control gate electrode formed on the block insulating film, wherein the tunnel insulating film comprises a first region which is formed on a surface of the semiconductor region and contains silicon and oxygen, a second region which contains silicon and nitrogen, a third region which is formed on a back surface of the charge-storage insulating film and contains silicon and oxygen, and an insulating region which is formed at least between the first region and the second region or between the second region and the third region, and contains silicon and nitrogen and oxygen and the second region is formed between the first region and the third region.Type: GrantFiled: December 15, 2009Date of Patent: August 28, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Masaaki Higuchi, Hiroshi Matsuba, Yoshio Ozawa, Tetsuya Kai
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Publication number: 20120086069Abstract: In one embodiment, a nonvolatile semiconductor memory device includes a substrate; a tunnel insulating film on the substrate; a charge storage layer on the tunnel insulating film; a block insulating film on the charge storage layer; a first element isolation insulating film in an element isolation trench in the substrate, having a bottom surface lower than an interface between the substrate and the tunnel insulating film, and having a top surface lower than an interface between the charge storage layer and the block insulating film; a second element isolation insulating film on the first element isolation insulating film, protruding to a top surface of the block insulating film, in contact with a side surface of the block insulating film, and having a higher Si concentration than the block insulating film; and a control gate electrode on the block insulating film and on the second element isolation insulating film.Type: ApplicationFiled: September 13, 2011Publication date: April 12, 2012Applicant: KABUSHIKI KAISHA TOSHIBAInventors: Tetsuya Kai, Yoshio Ozawa
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Patent number: 8115248Abstract: A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film.Type: GrantFiled: February 19, 2009Date of Patent: February 14, 2012Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kai, Ryuji Ohba, Yoshio Ozawa
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Publication number: 20120034754Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.Type: ApplicationFiled: October 13, 2011Publication date: February 9, 2012Applicant: Kabushiki Kaisha ToshibaInventors: Kazuaki Iwasawa, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
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Patent number: 8080463Abstract: A semiconductor device manufacturing method has forming element isolation trenches in a semiconductor substrate, forming a silicon compound film in insides of the element isolation trenches in order to embed the element isolation trenches, conducting a first oxidation processing at a first temperature to reform a surface of the silicon compound film to a volatile matter emission preventing layer which permits passage of an oxidizing agent and impurities and which does not permit passage of a volatile matter containing silicon atoms, and conducting a second oxidation processing at a second temperature which is higher than the first temperature to form a coated silicon oxide film inside the element isolation trenches.Type: GrantFiled: January 21, 2010Date of Patent: December 20, 2011Assignee: Kabushiki Kaisha ToshibaInventors: Kazuaki Iwasawa, Takeshi Hoshi, Keisuke Nakazawa, Shogo Matsuo, Takashi Nakao, Ryu Kato, Tetsuya Kai, Katsuyuki Sekine
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Publication number: 20110303969Abstract: According to one embodiment, a semiconductor memory device with memory cells each composed of a vertical transistor, comprises a silicon layer formed into a columnar shape on a silicon substrate, a gate insulating film part in which a tunnel insulating film, a charge storage layer, and a block insulating film are formed to surround the sidewall surface of the silicon layer, and a stacked structure part formed to surround the sidewall surface of the gate insulating film part and in which a plurality of interlayer insulating films and a plurality of control gate electrode layers are stacked alternately. The silicon layer, gate insulating film part, and control gate electrode layer constitute the vertical transistor. The charge storage layer has a region lower in trap level than a region facing the control gate electrode layer between the vertical transistors.Type: ApplicationFiled: March 21, 2011Publication date: December 15, 2011Inventors: Tetsuya KAI, Yoshio Ozawa, Ryota Fujitsuka, Yoshitaka Tsunashima
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Publication number: 20110175157Abstract: According to one embodiment, a nonvolatile semiconductor memory device includes a semiconductor layer; first and second insulating layers; a functional layer; first and second gate electrodes. The first insulating layer opposes the semiconductor layer. The second insulating layer is provided between the semiconductor layer and the first insulating layer. The functional layer is provided between the first and second insulating layers. The second gate electrode is separated from the first gate electrode. The first insulating layer is disposed between the first gate electrode and the semiconductor layer and between the second gate electrode and the semiconductor layer. The charge storabilities in first and second regions of the functional layer are different from that of a third region of the functional layer. The first and second regions oppose the first and second gate electrodes, respectively. The third region is between the first and the second regions.Type: ApplicationFiled: January 18, 2011Publication date: July 21, 2011Applicant: Kabushiki Kaisha ToshibaInventors: Katsuyuki SEKINE, Tetsuya Kai, Yoshio Ozawa
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Publication number: 20100237402Abstract: A first select transistor is formed on a semiconductor substrate. Memory cell transistors are stacked on the first select transistor and connected in series. A second select transistor is formed on the memory cell transistors. The memory cell transistors include a tapered semiconductor pillar which increases in diameter from the first select transistor toward the second select transistor, a tunnel dielectric film formed on the side surface of the semiconductor pillar, a charge storage layer which is formed on the side surface of the tunnel dielectric film and which increases in charge trap density from the first select transistor side toward the second select transistor side, a block dielectric film formed on the side surface of the charge storage layer, and conductor films which are formed on the side surface of the block dielectric film and which serve as gate electrodes.Type: ApplicationFiled: March 18, 2010Publication date: September 23, 2010Inventors: Katsuyuki SEKINE, Kensuke TAKANO, Masaaki HIGUCHI, Tetsuya KAI, Yoshio OZAWA
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Publication number: 20100213534Abstract: In a nonvolatile semiconductor memory device provided with memory cell transistors, each of the memory cell transistors has a tunnel insulating film, a floating gate electrode, an inter-electrode insulating film, and element isolation insulating films respectively. The floating gate electrode on the tunnel insulating film is provided with a first floating gate electrode and a second floating gate electrode formed sequentially from the bottom, the second floating gate electrode being narrower in a channel-width direction than the first one. Levels of upper surfaces of the element isolation insulating films and the first floating gate electrode are the same. The inter-electrode insulating film continuously covers the upper and side surfaces of the floating gate electrode and the upper surfaces of the element isolation insulating films, and is higher in a nitrogen concentration in a boundary portion to the floating gate electrode than in boundary portions to the element isolation insulating films.Type: ApplicationFiled: February 19, 2010Publication date: August 26, 2010Inventors: Katsuyuki SEKINE, Katsuaki Natori, Tetsuya Kai, Yoshio Ozawa
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Patent number: RE44630Abstract: A semiconductor device includes a semiconductor substrate, and a nonvolatile memory cell provided on the semiconductor substrate, the nonvolatile memory cell including a tunnel insulating film provided on a surface of the semiconductor substrate, the tunnel insulating film including semiconductor grains, the semiconductor grains included in both end portions of the tunnel insulating film having smaller grain size than the semiconductor grains included in other portions of the tunnel insulating film, a charge storage layer provided on the tunnel insulating film, an insulating film provided on the charge storage layer, and a control gate electrode provided on the insulating film.Type: GrantFiled: September 14, 2012Date of Patent: December 10, 2013Assignee: Kabushiki Kaisha ToshibaInventors: Tetsuya Kai, Ryuji Ohba, Yoshio Ozawa