Patents by Inventor Tetsuya Kajita

Tetsuya Kajita has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10243540
    Abstract: A digital filter includes: integration calculation units (10) that are cascade-connected, are fed time-division-multiplexed data, the time-division-multiplexed data being formed of pieces of data on M channels that are time-division multiplexed, the pieces of data on the respective channels being updated at a rate equal to a sampling frequency fs, operate in accordance with a clock having a frequency fs×M, and integrate the time-division-multiplexed data for every M samples; a frequency conversion unit (11) that operates in accordance with a clock having a frequency fD×M, decimates data at the sampling frequency fs input from the integration calculation unit (10) in the last stage at a sampling frequency fD, and delays data obtained as a result of decimation by (M?1) samples; and difference calculation units (12) that operate in accordance with the clock having the frequency fD×M, are cascade-connected to the output of the frequency conversion unit (11), and each subtract, from data input thereto, data M samp
    Type: Grant
    Filed: July 15, 2015
    Date of Patent: March 26, 2019
    Assignee: AZBIL CORPORATION
    Inventor: Tetsuya Kajita
  • Patent number: 10147952
    Abstract: The present invention relates to an electrode binder composition including a high-molecular-weight poly(amic acid) having a weight-average molecular weight of 5,000 or more and 100,000 or less and a low-molecular-weight poly(amic acid) having a weight-average molecular weight of 100 or more and 2,000 or less, and the present invention can provide an electrode binder composition that leads to a secondary battery having a high capacity superior in the initial charge/discharge efficiency and the cycle characteristics.
    Type: Grant
    Filed: June 3, 2014
    Date of Patent: December 4, 2018
    Assignee: NEC Corporation
    Inventors: Tetsuya Kajita, Shin Serizawa
  • Publication number: 20180212235
    Abstract: Provided are a lithium secondary battery wherein gas generation associated with charging and discharging can be suppressed even in case where silicon and silicon oxide are contained as negative electrode active materials, and wherein deformation due to the gas generation can be suppressed even in case where a resin film is used as an outer package; and a method for manufacturing the lithium secondary battery. A lithium secondary battery comprises a negative electrode containing a negative electrode active material, a positive electrode containing a positive electrode active material, and an electrolytic solution used to immerse the negative electrode active material and the positive electrode active material, wherein the negative electrode active material contains silicon and silicon oxide that have been subjected to a reduction treatment.
    Type: Application
    Filed: March 19, 2018
    Publication date: July 26, 2018
    Applicant: NEC Corporation
    Inventors: Tetsuya KAJITA, Jiro IRIYAMA, Shin SERIZAWA
  • Patent number: 10031539
    Abstract: An output circuit (10) according to the present invention includes a first output terminal (VO) and a second output terminal (SGND); an output transistor (MP1) connected between a first fixed-potential node (VCC) and the first output terminal; an output load (15) connected between the first output terminal and the second output terminal; a control circuit (13) that controls the output transistor so that a monitor voltage (VS) based on a voltage between the first output terminal and the second output terminal matches an input voltage (VI); a constant voltage source (16) whose one end is connected to the second terminal and whose other end is connected to a second fixed-potential node (GND); and a circuit (R4) that forms a current path between the first output terminal and the second fixed-potential node. Accordingly, in the output circuit, stability of a negative feedback loop can be enhanced, and linearity of an output voltage with respect to an input voltage can be enhanced.
    Type: Grant
    Filed: October 20, 2014
    Date of Patent: July 24, 2018
    Assignee: AZBIL CORPORATION
    Inventors: Taichiro Kato, Tetsuya Kajita
  • Patent number: 9973171
    Abstract: A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency fS that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency fS to reduce the sampling frequency fS to a sampling frequency fD=fS/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency fD and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: May 15, 2018
    Assignee: Azbil Corporation
    Inventor: Tetsuya Kajita
  • Patent number: 9960762
    Abstract: Disclosed is a startup circuit comprises a current path comprising a circuit including a P-channel MOS transistor, a P-channel MOS transistor, and an N-channel MOS transistor connected in series. After a constant current circuit is started, the N-channel MOS transistor is turned on, an operating current is fed through the current path, and an N-channel MOS transistor is turned off to cut off a startup current. After the startup current is cut off, the gate voltage of the P-channel MOS transistor is controlled by the voltage (bias voltage during operation of the constant current circuit) of a node, a drain-source voltage of the P-channel MOS transistor is reduced, and the operating current flowing through the current path is limited.
    Type: Grant
    Filed: August 31, 2015
    Date of Patent: May 1, 2018
    Assignee: Azbil Corporation
    Inventor: Tetsuya Kajita
  • Patent number: 9768476
    Abstract: A control system for a lithium secondary battery measures a voltage V of a negative electrode that uses silicon oxide as a negative electrode active material, with respect to a lithium reference electrode and a discharge capacity Q of the lithium secondary battery during discharge of the lithium secondary battery; generates a V?dQ/dV curve representing a relationship between dQ/dV, which is a proportion of an amount of change dQ in the discharge capacity Q to an amount of change dV in the voltage V, and the voltage V; calculates an intensity ratio of two peaks appearing on the V?dQ/dV curve for two voltage values in the voltage V; and senses a state of the negative electrode utilizing the intensity ratio.
    Type: Grant
    Filed: March 27, 2015
    Date of Patent: September 19, 2017
    Assignees: NEC CORPORATION, NEC ENERGY DEVICES, LTD.
    Inventors: Jiro Iriyama, Tetsuya Kajita, Daisuke Kawasaki, Ryuichi Kasahara, Tatsuji Numata
  • Publication number: 20170230044
    Abstract: Disclosed is a startup circuit comprises a current path comprising a circuit including a P-channel MOS transistor, a P-channel MOS transistor, and an N-channel MOS transistor connected in series. After a constant current circuit is started, the N-channel MOS transistor is turned on, an operating current is fed through the current path, and an N-channel MOS transistor is turned off to cut off a startup current. After the startup current is cut off, the gate voltage of the P-channel MOS transistor is controlled by the voltage (bias voltage during operation of the constant current circuit) of a node, a drain-source voltage of the P-channel MOS transistor is reduced, and the operating current flowing through the current path is limited.
    Type: Application
    Filed: August 31, 2015
    Publication date: August 10, 2017
    Applicant: Azbil Corporation
    Inventor: Tetsuya KAJITA
  • Publication number: 20170222627
    Abstract: A digital filter includes: integration calculation units (10) that are cascade-connected, are fed time-division-multiplexed data, the time-division-multiplexed data being formed of pieces of data on M channels that are time-division multiplexed, the pieces of data on the respective channels being updated at a rate equal to a sampling frequency fs, operate in accordance with a clock having a frequency fs×M, and integrate the time-division-multiplexed data for every M samples; a frequency conversion unit (11) that operates in accordance with a clock having a frequency fD×M, decimates data at the sampling frequency fs input from the integration calculation unit (10) in the last stage at a sampling frequency fD, and delays data obtained as a result of decimation by (M?1) samples; and difference calculation units (12) that operate in accordance with the clock having the frequency fD×M, are cascade-connected to the output of the frequency conversion unit (11), and each subtract, from data input thereto, data M samp
    Type: Application
    Filed: July 15, 2015
    Publication date: August 3, 2017
    Applicant: Azbil Corporation
    Inventor: Tetsuya KAJITA
  • Publication number: 20170201236
    Abstract: A digital filter includes integrator circuits configured to operate based on a clock of a sampling frequency fS that is equal to a sampling frequency of input data and determine a sum of the input data on a sample-by-sample basis, a frequency converter circuit configured to perform decimation on data of the sampling frequency fS to reduce the sampling frequency fS to a sampling frequency fD=fS/N, one or more differentiator circuits configured to operate based on a clock of the sampling frequency fD and subtract data of an immediately preceding sample from the input data, a differentiator circuit for removal of 50 Hz configured to operate based on the clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples, and a differentiator circuit for removal of 60 Hz configured to operate based on a clock of the sampling frequency fD and subtract, from the input data, data preceding the input data by a plurality of samples.
    Type: Application
    Filed: May 15, 2015
    Publication date: July 13, 2017
    Applicant: Azbil Corporation
    Inventor: Tetsuya KAJITA
  • Publication number: 20160320782
    Abstract: An output circuit (10) according to the present invention includes a first output terminal (VO) and a second output terminal (SGND); an output transistor (MP1) connected between a first fixed-potential node (VCC) and the first output terminal; an output load (15) connected between the first output terminal and the second output terminal; a control circuit (13) that controls the output transistor so that a monitor voltage (VS) based on a voltage between the first output terminal and the second output terminal matches an input voltage (VI); a constant voltage source (16) whose one end is connected to the second terminal and whose other end is connected to a second fixed-potential node (GND); and a circuit (R4) that forms a current path between the first output terminal and the second fixed-potential node. Accordingly, in the output circuit, stability of a negative feedback loop can be enhanced, and linearity of an output voltage with respect to an input voltage can be enhanced.
    Type: Application
    Filed: October 20, 2014
    Publication date: November 3, 2016
    Applicant: Azbil Corporation
    Inventors: Taichiro KATO, Tetsuya KAJITA
  • Publication number: 20160133935
    Abstract: The present invention relates to an electrode binder composition including a high-molecular-weight poly(amic acid) having a weight-average molecular weight of 5,000 or more and 100,000 or less and a low-molecular-weight poly(amic acid) having a weight-average molecular weight of 100 or more and 2,000 or less, and the present invention can provide an electrode binder composition that leads to a secondary battery having a high capacity superior in the initial charge/discharge efficiency and the cycle characteristics.
    Type: Application
    Filed: June 3, 2014
    Publication date: May 12, 2016
    Inventors: Tetsuya KAJITA, Shin SERIZAWA
  • Patent number: 9325010
    Abstract: Provided is a negative electrode active material for a lithium secondary cell, the material having the function of a binder for the active material, and being capable of stable reversible reactions with lithium. Also, provided are an extended-life lithium secondary cell having improved energy density and stable charge/discharge, and a method for producing the same. The negative electrode active material for a lithium secondary cell is polyimide represented by formula (1) (wherein R1 and R2 independently denote an alkyl, alkoxy, acyl, phenyl, or phenoxy group).
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: April 26, 2016
    Assignee: NEC Corporation
    Inventors: Jiro Iriyama, Tetsuya Kajita, Daisuke Kawasaki, Tatsuji Numata, Kazuhiko Inoue
  • Patent number: 9312534
    Abstract: Provided is a nonaqueous electrolytic solution secondary battery having a high energy density, and a positive electrode and a negative electrode used therefor. The nonaqueous electrolytic solution secondary battery includes a positive electrode and a negative electrode, wherein: the negative electrode contains a negative electrode active material having an initial charge/discharge efficiency of 75% or less when charged and discharged by employing metallic Li as a counter electrode; and the positive electrode contains a metal oxide (X) represented by AxMeOy (wherein A is Na and/or K, Me is Ni and/or Cu, x satisfies 1.9?x?2.1, and y satisfies 1.9?y?2.1).
    Type: Grant
    Filed: December 9, 2011
    Date of Patent: April 12, 2016
    Assignee: NEC CORPORATION
    Inventors: Tatsuji Numata, Hiroo Takahashi, Tetsuya Kajita
  • Patent number: 9263741
    Abstract: There is provided a negative electrode for a nonaqueous electrolyte secondary battery in which when a battery is formed, the energy density is high, and moreover, the decrease in charge and discharge capacity is small even if charge and discharge are repeated. By using silicon oxide particles having a particle diameter in a particular range as a starting raw material, and heating these particles in the range of 850° C. to 1050° C., Si microcrystals are deposited on the surfaces of the particles. Then, by performing doping of Li, a structure comprising a plurality of protrusions having height and cross-sectional area in a particular range is formed on the surfaces. The average value of the height of the above protrusions is 2% to 19% of the average particle diameter of the above lithium-containing silicon oxide particles.
    Type: Grant
    Filed: December 17, 2009
    Date of Patent: February 16, 2016
    Assignee: NEC Energy Devices, Ltd.
    Inventors: Jiro Iriyama, Ryuichi Kasahara, Tetsuya Kajita, Tatsuji Numata
  • Patent number: 9123928
    Abstract: The object of an exemplary embodiment of the invention is to provide a negative electrode having excellent cycle property. An exemplary embodiment of the invention a method for doping and dedoping lithium for the first time after a negative electrode for a lithium secondary battery comprising silicon oxide as an active material is produced, comprising doping the lithium within the following current value range (A) and within the following doped amount range (B); current value range (A): a range of a current value in which a doped amount in which only one peak appears at 1 V or less on the V-dQ/dV curve becomes maximum, wherein the V-dQ/dV curve represents a relationship between voltage V of the negative electrode with respect to a lithium reference electrode and dQ/dV that is a ratio of variation dQ of lithium dedoped amount Q in the negative electrode to variation dV of the voltage V, and doped amount range (B): a range of a doped amount in which only one peak appears at 1 V or less on the V-dQ/dV curve.
    Type: Grant
    Filed: April 6, 2012
    Date of Patent: September 1, 2015
    Assignee: NEC Corporation
    Inventors: Jiro Iriyama, Tetsuya Kajita, Daisuke Kawasaki, Tatsuji Numata
  • Publication number: 20150200425
    Abstract: There is provided a control system for a lithium secondary battery that can quantitatively sense a deterioration state inherent in a lithium secondary battery using silicon oxide as a negative electrode active material, that is, the nonuniform reaction state of a negative electrode.
    Type: Application
    Filed: March 27, 2015
    Publication date: July 16, 2015
    Applicants: NEC ENERGY DEVICES, LTD., NEC CORPORATION
    Inventors: Jiro IRIYAMA, Tetsuya KAJITA, Daisuke KAWASAKI, Ryuichi KASAHARA, Tatsuji NUMATA
  • Patent number: 9076995
    Abstract: A secondary battery according to the present exemplary embodiment is a secondary battery including a laminated electrode body provided with at least one pair of positive and negative electrodes and an outer enclosure that accommodates the laminated electrode body, wherein the outer enclosure includes one or more concave portions, inside a border corresponding to an outer edge of an electrode surface of an outermost layer of the laminated electrode body, on a surface facing the electrode surface, and wherein, when a band-shaped outer circumferential region having an area that is a half of an area inside the border is set inside the border, at least one of the concave portions is located inside the outer circumferential region.
    Type: Grant
    Filed: March 21, 2012
    Date of Patent: July 7, 2015
    Assignee: NEC CORPORATION
    Inventors: Shin Serizawa, Hiroo Takahashi, Daisuke Kawasaki, Jiro Iriyama, Ryuichi Kasahara, Emiko Fujii, Tetsuya Kajita, Tatsuji Numata
  • Patent number: 9018916
    Abstract: There is provided a control system for a lithium secondary battery that can quantitatively sense a deterioration state inherent in a lithium secondary battery using silicon oxide as a negative electrode active material, that is, the nonuniform reaction state of a negative electrode.
    Type: Grant
    Filed: July 20, 2011
    Date of Patent: April 28, 2015
    Assignees: NEC Corporation, NEC Energy Devices, Ltd.
    Inventors: Jiro Iriyama, Tetsuya Kajita, Daisuke Kawasaki, Ryuichi Kasahara, Tatsuji Numata
  • Publication number: 20150072220
    Abstract: Provided are a lithium secondary battery wherein gas generation associated with charging and discharging can be suppressed even in case where silicon and silicon oxide are contained as negative electrode active materials, and wherein deformation due to the gas generation can be suppressed even in case where a resin film is used as an outer package; and a method for manufacturing the lithium secondary battery. A lithium secondary battery comprises a negative electrode containing a negative electrode active material, a positive electrode containing a positive electrode active material, and an electrolytic solution used to immerse the negative electrode active material and the positive electrode active material, wherein the negative electrode active material contains silicon and silicon oxide that have been subjected to a reduction treatment.
    Type: Application
    Filed: March 22, 2013
    Publication date: March 12, 2015
    Applicant: NEC CORPORATION
    Inventors: Tetsuya Kajita, Jiro Iriyama, Shin Serizawa