Abstract: It is provided an information processing apparatus. The information processing apparatus includes a processor and memory storing an instruction for causing the processor to execute a first process and a second process exclusively in a process of an interrupt to Operating System (OS). The second process uses data related to a result of the first process. The processor further executes storing the data in memory which can be accessed by the OS and the process of the interrupt to the OS, and executing a process for instructing the OS to execute the second process.

Abstract: An information processing device includes a plurality of processors each of which is coupled to at least some of the plurality of processors. A first processor from among the plurality of processors is configured to calculate a plurality of communication paths between a second processor and a third processor from among the plurality of processors, identify a communication path that does not pass through a processor that is a target of dynamic reconfiguration, as a path to be used, from among the plurality of calculated communication paths, and transmit information on the identified path to be used, to a processor on the identified communication path. The processor that receives from the first processor the information on the identified path executes communication processing between the second processor and the third processor, by using the communication path that is indicated by the received information on the path to be used.

Abstract: An information processing device includes a plurality of processors each of which is coupled to at least some of the plurality of processors. A first processor from among the plurality of processors is configured to calculate a plurality of communication paths between a second processor and a third processor from among the plurality of processors, identify a communication path that does not pass through a processor that is a target of dynamic reconfiguration, as a path to be used, from among the plurality of calculated communication paths, and transmit information on the identified path to be used, to a processor on the identified communication path. The processor that receives from the first processor the information on the identified path executes communication processing between the second processor and the third processor, by using the communication path that is indicated by the received information on the path to be used.

Abstract: When an access from a virtual machine to a VGA is detected, a table managing identification information of a bridge on each path from a CPU to each VGA and passage setting information indicating whether or not to permit the passage of each path is referred to, and table information and a state of each bridge are set such that the passage of the path from the CPU to an SVGA to be accessed by the corresponding virtual machine is permitted, and the access is executed. Therefore, collision of I/O addresses can be avoided while maintaining the state of connecting a plurality of VGAs with fixed I/O addresses to a plurality of virtual machines.

Abstract: An information processing device includes a plurality of processors each of which is coupled to at least some of the plurality of processors. A first processor from among the plurality of processors is configured to calculate a plurality of communication paths between a second processor and a third processor from among the plurality of processors, identify a communication path that does not pass through a processor that is a target of dynamic reconfiguration, as a path to be used, from among the plurality of calculated communication paths, and transmit information on the identified path to be used, to a processor on the identified communication path. The processor that receives from the first processor the information on the identified path executes communication processing between the second processor and the third processor, by using the communication path that is indicated by the received information on the path to be used.

Abstract: An information processing device creates a management table of bridge addresses by allocating the bridge addresses to a plurality of bridges, respectively, and, when detecting one access to one device of a plurality of devices, refers to the management table, performs, based on the management table referred to, cancelling allocation of a bridge address of the bridge addresses and reallocating the bridge address to one or more of the plurality of bridges to enable execution of the one access, and updates the management table in regard to the bridge address cancelled and reallocated. Consequently, the information processing device can simultaneously use bridges the number of which exceeds a predetermined number even when the bridges the number of which exceeds the predetermined number are provided in the information processing device and therefore bridge addresses run out.

Abstract: When an access from a virtual machine to a VGA is detected, a table managing identification information of a bridge on each path from a CPU to each VGA and passage setting information indicating whether or not to permit the passage of each path is referred to, and table information and a state of each bridge are set such that the passage of the path from the CPU to an SVGA to be accessed by the corresponding virtual machine is permitted, and the access is executed. Therefore, collision of I/O addresses can be avoided while maintaining the state of connecting a plurality of VGAs with fixed I/O addresses to a plurality of virtual machines.