Patents by Inventor Tetsuya Koyama
Tetsuya Koyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10134680Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.Type: GrantFiled: August 14, 2017Date of Patent: November 20, 2018Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
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Publication number: 20170365559Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.Type: ApplicationFiled: August 14, 2017Publication date: December 21, 2017Inventors: Takaharu YAMANO, Hajime IIZUKA, Hideaki SAKAGUCHI, Toshio KOBAYASHI, Tadashi ARAI, Tsuyoshi KOBAYASHI, Tetsuya KOYAMA, Kiyoaki IIDA, Tomoaki MASHIMA, Koichi TANAKA, Yuji KUNIMOTO, Takashi YANAGISAWA
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Patent number: 9768122Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.Type: GrantFiled: August 19, 2016Date of Patent: September 19, 2017Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
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Publication number: 20160358858Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.Type: ApplicationFiled: August 19, 2016Publication date: December 8, 2016Inventors: Takaharu YAMANO, Hajime IIZUKA, Hideaki SAKAGUCHI, Toshio KOBAYASHI, Tadashi ARAI, Tsuyoshi KOBAYASHI, Tetsuya KOYAMA, Kiyoaki IIDA, Tomoaki MASHIMA, Koichi TANAKA, Yuji KUNIMOTO, Takashi YANAGISAWA
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Patent number: 9451702Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.Type: GrantFiled: July 1, 2014Date of Patent: September 20, 2016Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
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Publication number: 20160143139Abstract: An electronic component device includes a first insulating layer, a wiring layer, a second insulating layer, a wiring component, and first and second electronic components. The first insulating layer includes a mounting region on an upper surface thereof. The wiring layer is formed on the first insulating layer except the mounting region. The second insulating layer is formed on the first insulating layer, is formed with an opening in the mounting region, and is formed with first and second connection holes on the wiring layer. The wiring component is mounted in the mounting region and in the opening and includes first and second connecting portions. The first electronic component is connected to the first connecting portion and is connected to the wiring layer in the first connection hole. The second electronic component is connected to the second connecting portion and is connected to the wiring layer in second connection hole.Type: ApplicationFiled: November 11, 2015Publication date: May 19, 2016Inventors: Haruo Sorimachi, Tetsuya Koyama
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Patent number: 9257386Abstract: A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.Type: GrantFiled: November 20, 2014Date of Patent: February 9, 2016Assignee: Shinko Electric Industries Co., Ltd.Inventors: Hiromu Arisaka, Noriyoshi Shimizu, Masato Tanaka, Tetsuya Koyama, Akio Rokugawa
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Patent number: 9137900Abstract: An electronic component incorporated substrate includes a first substrate and a second substrate electrically connected to each other by a spacer unit. An electronic component is mounted on the first substrate and arranged between the first substrate and the second substrate. A first encapsulating resin is formed between the first substrate and the second substrate to encapsulate the electronic component. A second encapsulating resin is formed on a first surface of the first encapsulating resin to fill a space between the first encapsulating resin and the second substrate. The spacer unit includes a stacked structure of a first solder ball, a metal post, and a second solder ball stacked in a stacking direction of the first substrate and the second substrate.Type: GrantFiled: August 16, 2013Date of Patent: September 15, 2015Assignee: Shinko Electric Industries Co., Ltd.Inventors: Koichi Tanaka, Nobuyuki Kurashima, Hajime Iizuka, Tetsuya Koyama
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Patent number: 9097606Abstract: An imbalance correction method for correcting the imbalance of a rotor measures the vibration state of the rotor before temporary correction and the vibration state of the rotor after the temporary correction in a plurality of rotational speeds in order to make vibration values below the standard. An aggregation range of the tips of correction vectors for obtaining a vibration value which satisfies a vibration standard is calculated from vibration vectors in the rotational speeds. A real correction vector is selected from correction vectors having the tips in a region in which the aggregation ranges calculated for each of the rotational speeds overlap one another among a plurality of the correction vectors. A real correction amount and a real correction phase are set based on the real correction vector. The imbalance of the rotor is corrected based on the real correction amount and the real correction phase.Type: GrantFiled: August 31, 2011Date of Patent: August 4, 2015Assignee: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Nariyuki Kataoka, Tetsuya Koyama
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Publication number: 20150179560Abstract: A wiring substrate includes first and second wiring structures. The first wiring structure includes a core substrate, first and second insulation layers each formed from a thermosetting insulative resin including a reinforcement material, and a via wire formed in the first insulation layer. The second wiring structure includes a wiring layer formed on upper surfaces of the first insulation layer and the via wire, an insulation layer formed on the upper surface of the first insulation layer, and an uppermost wiring layer including a pad used to electrically connect a semiconductor chip and the wiring layer. An outermost insulation layer stacked on a lower surface of the second insulation layer exposes a portion of a lowermost wiring layer stacked on the lower surface of the second insulation layer as an external connection pad. The second wiring structure has a higher wiring density than the first wiring structure.Type: ApplicationFiled: November 20, 2014Publication date: June 25, 2015Inventors: Hiromu Arisaka, Noriyoshi SHIMIZU, Masato TANAKA, Tetsuya KOYAMA, Akio ROKUGAWA
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Patent number: 9059088Abstract: An electronic component built-in substrate, includes a lower wiring substrate, an electronic component mounted on the lower wiring substrate, an intermediate wiring substrate including an opening portion in which the electronic component is mounted, and arranged in a periphery of the electronic component, and connected to the lower wiring substrate via a first conductive ball, an upper wiring substrate arranged over the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second conductive ball, and a resin filled into respective areas between the lower wiring substrate, the intermediate wiring substrate, and the upper wiring substrate, and sealing the electronic component, wherein the first conductive ball and the second conductive ball are arranged in displaced positions mutually.Type: GrantFiled: July 17, 2013Date of Patent: June 16, 2015Assignee: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Nobuyuki Kurashima, Tetsuya Koyama, Hajime Ilzuka, Koichi Tanaka
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Publication number: 20150152004Abstract: To provide a laminate which is thin and light in weight, which has excellent gas barrier properties, flexibility and durability, and which is excellent in the flatness. A glass sheet/fluororesin laminate comprising a glass sheet having a thickness of from 10 to 500 ?m, and a fluororesin coated layer preferably having a thickness of from 0.1 to 1,000 ?m. Particularly, the thickness ratio of the fluororesin coated layer to the glass sheet is preferably from 0.001 to 10 by the fluororesin coated layer/the glass sheet. Further, the transmittance at a wavelength of from 400 to 700 nm is preferably at least 80%. Further, this laminate is suitable as a protective plate. Still further, this laminate is suitably applied to a photoelectric conversion element.Type: ApplicationFiled: February 5, 2015Publication date: June 4, 2015Inventors: Masahiro ITO, Hiromasa YAMAMOTO, Satoshi SHIRATORI, Tetsuya KOYAMA, Norihide SUGIYAMA, Koji KOGANEZAWA, Ryota NAKAJIMA
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Patent number: 8997526Abstract: A vacuum degassing apparatus for molten glass is comprised of an uprising pipe, a vacuum degassing vessel, a downfalling pipe, an upstream side pit that supplies molten glass to the uprising pipe, and a downstream side pit that receives molten glass from the downfalling pipe. The vacuum degassing apparatus for molten glass is further comprised of a separating mechanism that separates a part of molten glass moving from the downfalling pipe to the downstream side pit, and a returning pipe that returns separated molten glass to the upstream side pit.Type: GrantFiled: April 26, 2013Date of Patent: April 7, 2015Assignee: Asahi Glass Company, LimitedInventors: Toru Nishikawa, Hironobu Yamamichi, Tetsuya Koyama, Yuji Endo, Hajime Itoh
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Publication number: 20140313681Abstract: An electronic part embedded substrate is disclosed. The electronic part embedded substrate includes a first substrate, a second substrate, an electronic part, an electrically connecting member, and a sealing member. A method of producing an electronic part embedded substrate is also disclosed. The method includes mounting an electronic part onto a first substrate, laminating a second substrate on the first substrate through an electrically connecting member; and filling a space between the first substrate and the second substrate with a sealing member to seal the electronic part.Type: ApplicationFiled: July 1, 2014Publication date: October 23, 2014Inventors: Takaharu YAMANO, Hajime IIZUKA, Hideaki SAKAGUCHI, Toshio KOBAYASHI, Tadashi ARAI, Tsuyoshi KOBAYASHI, Tetsuya KOYAMA, Kiyoaki IIDA, Tomoaki MASHIMA, Koichi TANAKA, Yuji KUNIMOTO, Takashi YANAGISAWA
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Patent number: 8793868Abstract: A method of producing a chip embedded substrate is disclosed. This method comprises a first step of mounting a semiconductor chip on a first substrate on which a first wiring is formed; and a second step of joining the first substrate with a second substrate on which a second wiring is formed. In the second step, the semiconductor chip is encapsulated between the first substrate and the second substrate and electrical connection is made between the first wiring and the second wiring so as to form multilayered wirings connected to the semiconductor chip.Type: GrantFiled: June 23, 2011Date of Patent: August 5, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Takaharu Yamano, Hajime Iizuka, Hideaki Sakaguchi, Toshio Kobayashi, Tadashi Arai, Tsuyoshi Kobayashi, Tetsuya Koyama, Kiyoaki Iida, Tomoaki Mashima, Koichi Tanaka, Yuji Kunimoto, Takashi Yanagisawa
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Patent number: 8736053Abstract: A circuit substrate having a mounting surface on which a semiconductor chip is mounted and at least one connection pad formed on the mounting surface is connected to a support plate having at least one mounting portion with a diameter larger than a diameter of the connection pad, through a truncated-cone-shaped solder layer which is formed from at least one solder ball on the basis of a difference between the diameter of the mounting portion and the diameter of the connection pad.Type: GrantFiled: June 19, 2012Date of Patent: May 27, 2014Assignee: Shinko Electric Industries Co., Ltd.Inventors: Koichi Tanaka, Nobuyuki Kurashima, Hajime Iizuka, Tetsuya Koyama
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Publication number: 20140063768Abstract: An electronic component incorporated substrate includes a first substrate and a second substrate electrically connected to each other by a spacer unit. An electronic component is mounted on the first substrate and arranged between the first substrate and the second substrate. A first encapsulating resin is formed between the first substrate and the second substrate to encapsulate the electronic component. A second encapsulating resin is formed on a first surface of the first encapsulating resin to fill a space between the first encapsulating resin and the second substrate. The spacer unit includes a stacked structure of a first solder ball, a metal post, and a second solder ball stacked in a stacking direction of the first substrate and the second substrate.Type: ApplicationFiled: August 16, 2013Publication date: March 6, 2014Applicant: SHINKO ELECTRIC INDUSTRIES CO., LTD.Inventors: Koichi Tanaka, Nobuyuki KURASHIMA, Hajime IIZUKA, Tetsuya KOYAMA
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Publication number: 20140054773Abstract: An electronic component built-in substrate, includes a lower wiring substrate, an electronic component mounted on the lower wiring substrate, an intermediate wiring substrate including an opening portion in which the electronic component is mounted, and arranged in a periphery of the electronic component, and connected to the lower wiring substrate via a first conductive ball, an upper wiring substrate arranged over the electronic component and the intermediate wiring substrate, and connected to the intermediate wiring substrate via a second conductive ball, and a resin filled into respective areas between the lower wiring substrate, the intermediate wiring substrate, and the upper wiring substrate, and sealing the electronic component, wherein the first conductive ball and the second conductive ball are arranged in displaced positions mutually.Type: ApplicationFiled: July 17, 2013Publication date: February 27, 2014Inventors: Nobuyuki KURASHIMA, Tetsuya KOYAMA, Hajime IIZUKA, Koichi TANAKA
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Publication number: 20130233023Abstract: A vacuum degassing apparatus for molten glass is comprised of an uprising pipe, a vacuum degassing vessel, a downfalling pipe, an upstream side pit that supplies molten glass to the uprising pipe, and a downstream side pit that receives molten glass from the downfalling pipe. The vacuum degassing apparatus for molten glass is further comprised of a separating mechanism that separates a part of molten glass moving from the downfalling pipe to the downstream side pit, and a returning pipe that returns separated molten glass to the upstream side pit.Type: ApplicationFiled: April 26, 2013Publication date: September 12, 2013Applicant: Asahi Glass Company, LimitedInventors: Toru Nishikawa, Hironobu Yamamichi, Tetsuya Koyama, Yuji Endo, Hajime Itoh
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Publication number: 20130174658Abstract: An imbalance correction method for correcting the imbalance of a rotor measures the vibration state of the rotor before temporary correction and the vibration state of the rotor after the temporary correction in a plurality of rotational speeds in order to make vibration values below the standard. An aggregation range of the tips of correction vectors for obtaining a vibration value which satisfies a vibration standard is calculated from vibration vectors in the rotational speeds. A real correction vector is selected from correction vectors having the tips in a region in which the aggregation ranges calculated for each of the rotational speeds overlap one another among a plurality of the correction vectors. A real correction amount and a real correction phase are set based on the real correction vector. The imbalance of the rotor is corrected based on the real correction amount and the real correction phase.Type: ApplicationFiled: August 31, 2011Publication date: July 11, 2013Applicant: KABUSHIKI KAISHA TOYOTA JIDOSHOKKIInventors: Nariyuki Kataoka, Tetsuya Koyama