Patents by Inventor Tetsuya Maruyama

Tetsuya Maruyama has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 6826577
    Abstract: Provided are a method and apparatus having simplified operation for data storage according to which data, for example, images contained in a home page, are stored in a computer system, and a recording medium employed in the method and apparatus. The computer system stores images contained in a home page that is composed of character information and image information and that is displayed in a screen. Herein, a document describing the home page and written in a given language is read. Source files of storable images contained in the home page are retrieved from the document. Image information of the images is listed based on the retrieved source files. A desired image is selected from the listed image information. The selected image is then stored on a recording medium.
    Type: Grant
    Filed: February 8, 1999
    Date of Patent: November 30, 2004
    Assignee: Fujitsu Limited
    Inventors: Tetsuya Maruyama, Naoko Miyagi
  • Patent number: 6806726
    Abstract: A semiconductor integrated circuit is segmented into a plurality of blocks. Each block includes a switching transistor which is connected between the CMOS circuit of the block and the ground point and is adapted to shut off the current of the CMOS circuit by being controlled by a test mode control signal, and a leakage current detecting circuit which has a self-check function for the block. A signal which is the logical sum of the outputs of the leakage current detecting circuits of all blocks is the led out of the semiconductor integrated circuit through a common external output terminal.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: October 19, 2004
    Assignee: Renesas Technology Corp.
    Inventors: Hidehiro Okada, Tetsuya Maruyama
  • Publication number: 20040150419
    Abstract: A semiconductor integrated circuit is segmented into a plurality of blocks. Each block includes a switching transistor which is connected between the CMOS circuit of the block and the ground point and is adapted to shut off the current of the CMOS circuit by being controlled by a test mode control signal, and a leakage current detecting circuit which has a self-check function for the block. A signal which is the logical sum of the outputs of the leakage current detecting circuits of all blocks is led out of the semiconductor integrated circuit through a common external output terminal.
    Type: Application
    Filed: December 30, 2003
    Publication date: August 5, 2004
    Inventors: Hidehiro Okada, Tetsuya Maruyama
  • Patent number: 6693448
    Abstract: A semiconductor integrated circuit is segmented into a plurality of blocks. Each block includes a switching transistor which is connected between the CMOS circuit of the block and the ground point and is adapted to shut off the current of the CMOS circuit by being controlled by a test mode control signal, and a leakage current detecting circuit which has a self-check function for the block. A signal which is the logical sum of the outputs of the leakage current detecting circuits of all blocks is led out of the semiconductor integrated circuit through a common external output terminal.
    Type: Grant
    Filed: February 23, 2001
    Date of Patent: February 17, 2004
    Assignee: Renesas Technology Corporation
    Inventors: Hidehiro Okada, Tetsuya Maruyama
  • Patent number: 6646464
    Abstract: A semiconductor integrated circuit technology that does not invite the drop of &agr;-ray resistance of flip-flop circuits even when devices are miniaturized. A data hold circuit according to this semiconductor integrated circuit technology includes at least three flip-flop circuits using the same signal as an input, and a majority logic circuit for outputting a signal in accordance with a logic value of the majority of the output of these flip-flop circuits.
    Type: Grant
    Filed: December 18, 2001
    Date of Patent: November 11, 2003
    Assignee: Hitachi, Ltd.
    Inventor: Tetsuya Maruyama
  • Publication number: 20020074609
    Abstract: A semiconductor integrated circuit technology that does not invite the drop of &agr;-ray resistance of flip-flop circuits even when devices are miniaturized. A data hold circuit according to this semiconductor integrated circuit technology includes at least three flip-flop circuits using the same signal as an input, and a majority logic circuit for outputting a signal in accordance with a logic value of the majority of the output of these flip-flop circuits.
    Type: Application
    Filed: December 18, 2001
    Publication date: June 20, 2002
    Applicant: Hitachi, Ltd.
    Inventor: Tetsuya Maruyama