Patents by Inventor Tetsuya Miyazawa

Tetsuya Miyazawa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10748763
    Abstract: An n?-type epitaxial layer is grown on a front surface of the silicon carbide substrate by a CVD method in a mixed gas atmosphere containing a source gas, a carrier gas, a doping gas, an additive gas, and a gas containing vanadium. The doping gas is nitrogen gas; and the gas containing vanadium is vanadium tetrachloride gas. In the mixed gas atmosphere, the vanadium bonds with the nitrogen, producing vanadium nitride, whereby the nitrogen concentration in the mixed gas atmosphere substantially decreases. As a result, the nitrogen taken in by the n?-type epitaxial layer decreases and the n?-type epitaxial layer including nitrogen and vanadium as dopants is grown having a low impurity concentration.
    Type: Grant
    Filed: August 30, 2018
    Date of Patent: August 18, 2020
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Tetsuya Miyazawa
  • Patent number: 10453924
    Abstract: A silicon carbide semiconductor substrate, including a silicon carbide substrate of a first conductivity type, a buffer layer of the first conductivity type and an epitaxial layer of the first conductivity type. The silicon carbide substrate has a central part and a peripheral part surrounding the central part, and is doped with a first impurity that determines the first conductivity type. The buffer layer is provided on a front surface of the central part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is at least 1.0×1018/cm3, and a second impurity different from the first impurity. The epitaxial layer is provided on a front surface of the peripheral part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is lower than the concentration of the first impurity in the buffer layer.
    Type: Grant
    Filed: June 26, 2018
    Date of Patent: October 22, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi Tawara, Hidekazu Tsuchida, Tetsuya Miyazawa
  • Patent number: 10354867
    Abstract: A method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a silicon carbide voltage-blocking-layer, the method includes: epitaxially growing a buffer layer on the substrate, doping a main dopant for determining a conductivity type of the buffer layer and doping an auxiliary dopant for capturing minority carriers in the buffer layer at a doping concentration less than the doping concentration of the main dopant, so that the buffer layer enhances capturing and extinction of the minority carriers, the minority carriers flowing in a direction from the voltage-blocking-layer to the substrate, so that the buffer layer has a lower resistivity than the voltage-blocking-layer, and so that the buffer layer includes silicon carbide as a main component; and epitaxially growing the voltage-blocking-layer on the buffer layer.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: July 16, 2019
    Assignee: FUJI ELECTRIC CO., LTD.
    Inventors: Hidekazu Tsuchida, Tetsuya Miyazawa, Yoshiyuki Yonezawa, Tomohisa Kato, Kazutoshi Kojima, Takeshi Tawara, Akihiro Otsuki
  • Publication number: 20190103271
    Abstract: An n?-type epitaxial layer is grown on a front surface of the silicon carbide substrate by a CVD method in a mixed gas atmosphere containing a source gas, a carrier gas, a doping gas, an additive gas, and a gas containing vanadium. The doping gas is nitrogen gas; and the gas containing vanadium is vanadium tetrachloride gas. In the mixed gas atmosphere, the vanadium bonds with the nitrogen, producing vanadium nitride, whereby the nitrogen concentration in the mixed gas atmosphere substantially decreases. As a result, the nitrogen taken in by the n?-type epitaxial layer decreases and the n?-type epitaxial layer including nitrogen and vanadium as dopants is grown having a low impurity concentration.
    Type: Application
    Filed: August 30, 2018
    Publication date: April 4, 2019
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi TAWARA, Hidekazu TSUCHIDA, Tetsuya MIYAZAWA
  • Publication number: 20180323263
    Abstract: A silicon carbide semiconductor substrate, including a silicon carbide substrate of a first conductivity type, a buffer layer of the first conductivity type and an epitaxial layer of the first conductivity type. The silicon carbide substrate has a central part and a peripheral part surrounding the central part, and is doped with a first impurity that determines the first conductivity type. The buffer layer is provided on a front surface of the central part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is at least 1.0×1018/cm3, and a second impurity different from the first impurity. The epitaxial layer is provided on a front surface of the peripheral part of the silicon carbide substrate, and is doped with the first impurity, of which a concentration is lower than the concentration of the first impurity in the buffer layer.
    Type: Application
    Filed: June 26, 2018
    Publication date: November 8, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Takeshi TAWARA, Hidekazu TSUCHIDA, Tetsuya MIYAZAWA
  • Publication number: 20180012758
    Abstract: A method for manufacturing an epitaxial wafer comprising a silicon carbide substrate and a silicon carbide voltage-blocking-layer, the method includes: epitaxially growing a buffer layer on the substrate, doping a main dopant for determining a conductivity type of the buffer layer and doping an auxiliary dopant for capturing minority carriers in the buffer layer at a doping concentration less than the doping concentration of the main dopant, so that the buffer layer enhances capturing and extinction of the minority carriers, the minority carriers flowing in a direction from the voltage-blocking-layer to the substrate, so that the buffer layer has a lower resistivity than the voltage-blocking-layer, and so that the buffer layer includes silicon carbide as a main component; and epitaxially growing the voltage-blocking-layer on the buffer layer.
    Type: Application
    Filed: September 22, 2017
    Publication date: January 11, 2018
    Applicant: FUJI ELECTRIC CO., LTD.
    Inventors: Hidekazu TSUCHIDA, Tetsuya MIYAZAWA, Yoshiyuki YONEZAWA, Tomohisa KATO, Kazutoshi KOJIMA, Takeshi TAWARA, Akihiro OTSUKl
  • Patent number: 9496345
    Abstract: The present invention provides a semiconductor structure which includes at least a p-type silicon carbide single crystal layer having an ?-type crystal structure, containing aluminum at impurity concentration of 1×1019 cm?3 or higher, and having thickness of 50 ?m or greater. Further provided is a method for producing the semiconductor structure of the present invention which method includes at least epitaxial growth step of introducing silicon carbide source and aluminum source and epitaxially growing p-type silicon carbide single crystal layer over a base layer made of silicon carbide single crystal having ?-type crystal structure, wherein the epitaxial growth step is performed at temperature conditions of from 1,500° C. to 1,700° C., and pressure conditions of from 5×103 Pa to 25×103 Pa.
    Type: Grant
    Filed: July 31, 2013
    Date of Patent: November 15, 2016
    Assignees: NATIONAL INSTITUTE OF ADVANCED INDUSTRIAL SCIENCE AND TECHNOLOGY, CENTRAL RESEARCH INSTITUTE OF ELECTRIC POWER INDUSTRY
    Inventors: Kazutoshi Kojima, Shiyang Ji, Tetsuya Miyazawa, Hidekazu Tsuchida, Koji Nakayama, Tetsuro Hemmi, Katsunori Asano
  • Publication number: 20150214306
    Abstract: The present invention provides a semiconductor structure which includes at least a p-type silicon carbide single crystal layer having an ?-type crystal structure, containing aluminum at impurity concentration of 1×1019 cm?3 or higher, and having thickness of 50 ?m or greater. Further provided is a method for producing the semiconductor structure of the present invention which method includes at least epitaxial growth step of introducing silicon carbide source and aluminum source and epitaxially growing p-type silicon carbide single crystal layer over a base layer made of silicon carbide single crystal having ?-type crystal structure, wherein the epitaxial growth step is performed at temperature conditions of from 1,500° C. to 1,700° C., and pressure conditions of from 5×103 Pa to 25×103 Pa.
    Type: Application
    Filed: July 31, 2013
    Publication date: July 30, 2015
    Inventors: Kazutoshi Kojima, Shiyang Ji, Tetsuya Miyazawa, Hidekazu Tsuchida, Koji Nakayama, Tetsuro Hemmi, Katsunori Asano
  • Publication number: 20070267008
    Abstract: A method of hydrolyzing an organic compound (in particular, polysaccharides such as starch, guar gum, or cellulose), characterized in that the hydrothermal reaction is performed in hot water with a pressure of 5 to 100 MPa and a temperature of 140 to 300° C., containing carbon dioxide being added by pressure application.
    Type: Application
    Filed: November 19, 2004
    Publication date: November 22, 2007
    Applicant: TAMA-TLO CORPORATION
    Inventors: Toshitaka Funazukuri, Tetsuya Miyazawa
  • Patent number: 7046148
    Abstract: Electronic tags are directly attached to commodities to be transported one by one. Gate terminals are installed on buildings or sites of traders long a distribution channel of the commodities. The electronic tag detects the commodity temperature and records it at intervals. When the commodity passes near the gate terminal, the information of the commodity temperature is transmitted to the gate terminal through the wireless communication. If the received information shows failure of the temperature control, the gate terminal output a warning.
    Type: Grant
    Filed: June 17, 2004
    Date of Patent: May 16, 2006
    Assignee: Fujitsu Limited
    Inventor: Tetsuya Miyazawa
  • Publication number: 20050140509
    Abstract: Electronic tags are directly attached to commodities to be transported one by one. Gate terminals are installed on buildings or sites of traders long a distribution channel of the commodities. The electronic tag detects the commodity temperature and records it at intervals. When the commodity passes near the gate terminal, the information of the commodity temperature is transmitted to the gate terminal through the wireless communication. If the received information shows failure of the temperature control, the gate terminal output a warning.
    Type: Application
    Filed: June 17, 2004
    Publication date: June 30, 2005
    Inventor: Tetsuya Miyazawa