Patents by Inventor Tetsuya Nakatsuka

Tetsuya Nakatsuka has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11244877
    Abstract: Provided is a sealing structure including a housing that houses a heat generating member or a heat dissipation member thereinside, and a resin that is filled in the housing. In a sectional view, the housing includes a first recess portion in a position facing the heat generating member or the heat dissipation member.
    Type: Grant
    Filed: April 4, 2016
    Date of Patent: February 8, 2022
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Nakatsuka, Shinya Kawakita, Susumu Ishida, Isamu Yoshida, Osamu Ikeda
  • Publication number: 20200303272
    Abstract: Provided is a sealing structure including a housing that houses a heat generating member or a heat dissipation member thereinside, and a resin that is filled in the housing. In a sectional view, the housing includes a first recess portion in a position facing the heat generating member or the heat dissipation member.
    Type: Application
    Filed: April 4, 2016
    Publication date: September 24, 2020
    Inventors: Tetsuya NAKATSUKA, Shinya KAWAKITA, Susumu ISHIDA, Isamu YOSHIDA, Osamu IKEDA
  • Patent number: 8907475
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: June 21, 2013
    Date of Patent: December 9, 2014
    Assignee: Renesas Electronics Corporation
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Patent number: 8699187
    Abstract: A manufacturing method for a head-stack assembly. The method includes preparing a head-stack assembly. The method further includes placing a connection pad forming surface of a connector tab formed on an end of the trace so as to be positioned opposite to an edge of a circuit board; sliding an elastic component along a backside of the connection pad forming surface; and, stopping the elastic component on the backside and pressing the backside with the elastic component so as to press the connection pad forming surface against the edge. In addition, the method includes metal-joining the connector tab and a connection pad of the circuit board by applying heat to a connection pad of the connector tab and the connection pad on the circuit board while pressing the connection pad forming surface against the edge with the elastic component; and, removing the elastic component after the metal-joining.
    Type: Grant
    Filed: December 18, 2009
    Date of Patent: April 15, 2014
    Assignee: HGST Netherlands B.V.
    Inventors: Tetsuya Nakamura, Takahiro Sakai, Masahiko Katoh, Yasushi Inoue, Tetsuya Nakatsuka, Satoshi Kaneko, Masashi Okubo
  • Publication number: 20130286621
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Application
    Filed: June 21, 2013
    Publication date: October 31, 2013
    Inventors: Hanae SHIMOKAWA, Tasao SOGA, Hiroaki OKUDAIRA, Toshiharu ISHIDA, Tetsuya NAKATSUKA, Yoshiharu INABA, Asao NISHIMURA
  • Patent number: 8503189
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: May 4, 2010
    Date of Patent: August 6, 2013
    Assignee: Renesas Electronics Corporation
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Patent number: 8179631
    Abstract: Embodiments of the present invention help to achieve a solder joining structure having high reliability, in which even if a componential material of a flange of a feed-through of a sealed magnetic disk drive is an iron-based material such as Kovar™, and a componential material of a base of the drive is an aluminum-based alloy, leakage of low-density gas is dramatically reduced. According to one embodiment, a base has a stepped portion in the inside of a periphery of an opening, and an inclined surface extending to the outside of the base is formed at an edge of a surface of the stepped portion, on which a flange of a feed-through is placed, thereby when the stepped portion of the base is joined by soldering with the flange of the feed-through, a solder fillet is formed not only in the inside of the base, but also in the outside thereof.
    Type: Grant
    Filed: April 21, 2008
    Date of Patent: May 15, 2012
    Assignee: Hitachi Global Storage Technologies Netherlands B.V.
    Inventors: Akihiko Aoyagi, Teruhiro Nakamiya, Takashi Kouno, Hitoshi Shindo, Tetsuya Nakatsuka
  • Patent number: 8022551
    Abstract: Each of junctions formed between a semiconductor device and a substrate comprises metal balls of Cu, or other materials and compounds of Sn and the metal balls, and the metal balls are bonded together by the compounds.
    Type: Grant
    Filed: April 7, 2006
    Date of Patent: September 20, 2011
    Assignee: Renesas Electronics Corporation
    Inventors: Tasao Soga, Hanae Shimokawa, Tetsuya Nakatsuka, Kazuma Miura, Mikio Negishi, Hirokazu Nakajima, Tsuneo Endoh
  • Patent number: 8020747
    Abstract: Along with miniaturization of a solder connection portion in a bump repair or a local reflow, a void generated at the time of soldering remains in a solder to remarkably reduce connection strength, and there occurs a non-connection phenomenon in which the solder connection portion and a solder paste are melted, but are not fused with each other. During melting of a solder, a target component is clamped, ultrasonic oscillation is directly applied only to the target component. Further, start of solidification of the solder connection portion is detected by change of an electric impedance of a transducer while applying the ultrasonic oscillation, and the clamp is released before a substrate is warped.
    Type: Grant
    Filed: July 7, 2009
    Date of Patent: September 20, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Nakatsuka, Masato Nakamura
  • Publication number: 20110109996
    Abstract: A manufacturing method for a head-stack assembly. The method includes preparing a head-stack assembly. The method further includes placing a connection pad forming surface of a connector tab formed on an end of the trace so as to be positioned opposite to an edge of a circuit board; sliding an elastic component along a backside of the connection pad forming surface; and, stopping the elastic component on the backside and pressing the backside with the elastic component so as to press the connection pad forming surface against the edge. In addition, the method includes metal joining the connector tab and a connection pad of the circuit board by applying heat to a connection pad of the connector tab and the connection pad on the circuit board while pressing the connection pad forming surface against the edge with the elastic component; and, removing the elastic component after the metal joining.
    Type: Application
    Filed: December 18, 2009
    Publication date: May 12, 2011
    Inventors: Tetsuya Nakamura, Takahiro Sakai, Masahiko Katoh, Yasushi Inoue, Tetsuya Nakatsuka, Satoshi Kaneko, Masashi Okubo
  • Patent number: 7911062
    Abstract: The present invention proposes a semiconductor device including a semiconductor chip having a plurality of electrodes, a plurality of leads electrically connected to the plurality of electrodes of the semiconductor chip by bonding wires, and a resin for implementing the semiconductor chip, wherein the plurality of leads are comprised of two or more kinds of leads having different rigidities.
    Type: Grant
    Filed: February 2, 2007
    Date of Patent: March 22, 2011
    Assignee: Hitachi, Ltd.
    Inventors: Tetsuya Nakatsuka, Koji Serizawa
  • Publication number: 20100328815
    Abstract: Due to a difference in coefficient of linear expansion between the constituent material of the flange and the constituent material of the base of the feedthrough, the solder material which joins these materials is unable to withstand the thermomechanical loading that is generated between these heterogeneous materials during their actual usage for a long period and, as a result, cracks formed in the solder-joined portion therebetween create low-density gas leakage paths that reduce actual lifespan to less than 5 years. Disclosed is a magnetic disk device comprising a magnetic disk, a magnetic head for recording and reproducing information onto and from the magnetic disk, a base, a feedthrough solder-joined to the base, and a solder-joined portion for joining the base and the feedthrough, wherein a recess portion is provided in the perimeter edge of the solder-joined portion of the base.
    Type: Application
    Filed: January 29, 2009
    Publication date: December 30, 2010
    Applicant: Hitachi, Ltd.
    Inventors: Tetsuya Nakatsuka, Masato Nakamura, Satoshi Kaneko
  • Publication number: 20100214753
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Application
    Filed: May 4, 2010
    Publication date: August 26, 2010
    Inventors: Hanae SHIMOKAWA, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Patent number: 7722962
    Abstract: A solder foil formed from a material comprising particles of Cu, etc. as metal particles and Sn particles as solder particles by rolling is suitable for solder bonding at a high temperature side in temperature-hierarchical bonding, and semiconductor devices and electronic devices produced by use of such solder bonding have distinguished reliability of mechanical characteristics, etc.
    Type: Grant
    Filed: December 19, 2001
    Date of Patent: May 25, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Tasao Soga, Hanae Hata, Toshiharu Ishida, Kanko Ishida, legal representative, Tetsuya Nakatsuka, Masahide Okamoto, Kazuma Miura
  • Patent number: 7709746
    Abstract: Provided are a bonded structure by a lead-free solder and an electronic article comprising the bonded structure. The bonded structure has a stable bonding interface with respect to a change in process of time, an enough strength and resistance to occurrence of whiskers while keeping good wettability of the solder. In the bonded structure, a lead-free Sn—Ag—Bi alloy solder is applied to an electrode through an Sn—Bi alloy layer. The Sn—Bi alloy, preferably, comprises 1 to 20 wt % Bi in order to obtain good wettability of the solder. In order to obtain desirable bonding characteristics having higher reliability in the invention, a copper layer is provided under the Sn—Bi alloy layer thereby obtaining an enough bonding strength.
    Type: Grant
    Filed: January 13, 2006
    Date of Patent: May 4, 2010
    Assignee: Renesas Technology Corp.
    Inventors: Hanae Shimokawa, Tasao Soga, Hiroaki Okudaira, Toshiharu Ishida, Tetsuya Nakatsuka, Yoshiharu Inaba, Asao Nishimura
  • Publication number: 20100006624
    Abstract: Along with miniaturization of a solder connection portion in a bump repair or a local reflow, a void generated at the time of soldering remains in a solder to remarkably reduce connection strength, and there occurs a non-connection phenomenon in which the solder connection portion and a solder paste are melted, but are not fused with each other. During melting of a solder, a target component is clamped, ultrasonic oscillation is directly applied only to the target component. Further, start of solidification of the solder connection portion is detected by change of an electric impedance of a transducer while applying the ultrasonic oscillation, and the clamp is released before a substrate is warped.
    Type: Application
    Filed: July 7, 2009
    Publication date: January 14, 2010
    Inventors: Tetsuya Nakatsuka, Masato Nakamura
  • Publication number: 20080259503
    Abstract: Embodiments of the present invention help to achieve a solder joining structure having high reliability, in which even if a componential material of a flange of a feed-through of a sealed magnetic disk drive is an iron-based material such as kovar, and a componential material of a base of the drive is an aluminum-based alloy, leakage of low-density gas is dramatically reduced. According to one embodiment, a base has a stepped portion in the inside of a periphery of an opening, and an inclined surface extending to the outside of the base is formed at an edge of a surface of the stepped portion, on which a flange of a feed-through is placed, thereby when the stepped portion of the base is joined by soldering with the flange of the feed-through, a solder fillet is formed not only in the inside of the base, but also in the outside thereof.
    Type: Application
    Filed: April 21, 2008
    Publication date: October 23, 2008
    Inventors: Akihiko Aoyagi, Teruhiro Nakamiya, Takashi Kouno, Hitoshi Shindo, Tetsuya Nakatsuka
  • Publication number: 20080261001
    Abstract: Disclosed is a low thermal resistance surface mount component and a mounting substrate bump-connected therewith, capable of removing a soldered low thermal resistance surface mount component from a circuit board without harming the performance of the circuit board or the performance of the low thermal resistance surface mount component. The solder bumps 3 in an area approaching the periphery 2 of the low thermal resistance surface mount component 1 are composed of a solder of a melting point lower than that of the solder bumps 3 in an area approaching the center. The low thermal resistance surface mount component 1 on the circuit board can be removed by partial heating and by melting the solder bumps. However, when the component is partially heated in this manner, the heating temperature declines approaching the periphery compared to that of the center of the low thermal resistance surface mount component 1.
    Type: Application
    Filed: February 28, 2005
    Publication date: October 23, 2008
    Inventors: Tetsuya Nakatsuka, Koji Serizawa, Shosaku Ishihara, Toshio Saeki
  • Publication number: 20080062665
    Abstract: There is proposed a mounting structure including a plurality of components each having a plurality of solder bumps, a substrate having a plurality of lands, and a solder connecting portion for connecting the solder bump and the land, wherein the land provided in an outer peripheral portion of the substrate is smaller than that of the land in a central portion of the substrate.
    Type: Application
    Filed: July 27, 2007
    Publication date: March 13, 2008
    Inventors: TETSUYA NAKATSUKA, Koji Serizawa
  • Publication number: 20070210139
    Abstract: The present invention proposes a semiconductor device including a semiconductor chip having a plurality of electrodes, a plurality of leads electrically connected to the plurality of electrodes of the semiconductor chip by bonding wires, and a resin for implementing the semiconductor chip, wherein the plurality of leads are comprised of two or more kinds of leads having different rigidities.
    Type: Application
    Filed: February 2, 2007
    Publication date: September 13, 2007
    Inventors: Tetsuya NAKATSUKA, Koji Serizawa