Abstract: A semiconductor memory device which employs a double word line system and a negative potential word line system wherein a lowered maximum applied voltage between a gate and a source and between the gate and a drain is used has a sub-word line driving circuit mounted along a main word line and having one transistor controlled so as to be always in the ON state, and which is disposed between another transistor and a sub-word line to control the sub-word line to a positive potential. A threshold voltage of two transistors to control the sub-word line to a negative potential is set so that they are held in the OFF state, when the sub-word is selected. When the sub-word line is not selected, a positive voltage being lower than the above-predetermined positive voltage is applied to their gates.

Abstract: In a nonvolatile semiconductor memory device including memory cells, a predetermined number of the memory cells are simultaneously erased. Only when at least one of the memory cells is overerased, i.e., is in a depletion state, a threshold voltage recovering operation is performed upon all of the memory cells, to relieve the overerased memory cell and suppress the deviation of threshold voltage.

Abstract: An electrically erasable and programmable read only memory device is equipped with a supply voltage switching circuit responsive to a write enable signal for selectively supplying a write-in voltage and a read-out voltage through a power distribution line to a row address decoder unit, and the supply voltage switching circuit includes a series of first and second p-channel enhancement type field effect transistors having respective gate electrodes coupled to the write-in voltage line and the power distribution line, a third p-channel enhancement type field effect transistor having a gate electrode coupled to the power distribution line and a controlling sub-circuit responsive to the write enable signal so as to supply first and second control signals of the ground level and a third control signal of the potential level equal to the power distribution line to the first and second p-channel enhancement type field effect transistors and the third p-channel enhancement type field effect transistor when the write

Abstract: A nonvolatile ferroelectric memory device comprises a power supply and a memory cell array having a plurality of memory cells arranged in rows and columns and further comprises a plate-voltage level generator, a power supply voltage detector, and a protective control circuit. The plate-voltage level generator generates a plate voltage on a plate line connected to the one electrode of a ferroelectric capacitor of each memory cell. The power supply voltage detector detects a voltage of the power supply to generate a low-voltage detection signal when the power supply voltage is lower than a threshold voltage. The protective control circuit responsive to the low-voltage detection signal fixes the word lines at a grounding voltage level so as to protect the ferroelectric capacitor from a voltage change of the word line. The protective control circuit may fix the bit lines at the plate voltage level when the power supply voltage is lower than the threshold voltage.