Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.

Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.

Abstract: A bonded assembly includes a memory die including a three-dimensional memory array located on a first single crystalline semiconductor substrate, and a logic die including a peripheral circuitry located on a second single crystalline semiconductor substrate and bonded to the memory die. The three-dimensional memory array includes word lines and bit lines. The logic die includes field effect transistors having semiconductor channels configured to flow electrical current along a channel direction that is parallel to the bit lines or word lines. Different crystallographic orientations are used for the first and second single crystalline semiconductor substrates. The crystallographic orientations of the first single crystalline semiconductor substrate are selected to minimize stress deformation of the memory chip, while the crystallographic orientations of the second single crystalline semiconductor substrate are selected to maximize device performance of the peripheral circuitry.

Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.

Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.

Abstract: A polishing pad includes a first pad portion and a second pad portion disposed therearound, and each of the first and second pad portions is replaced individually. A CMP apparatus with the polishing pad (first and second pad portions) attached thereto conducts polishing of a semiconductor wafer. The second pad portion is replaced with a replacement second pad portion when the total polishing time reaches a predetermined period of time.

Abstract: A method for manufacturing a semiconductor device, including depositing an interconnect material including Cu or Cu alloy over an insulating film, and polishing the interconnect material by CMP with a polishing liquid, wherein the oxidation-reduction potential (ORP) of the polishing liquid is controlled so as to be in the range of 400 mV to 700 mV vs. Ag/AgCl.

Abstract: A method for fabricating a semiconductor device includes: supporting a semiconductor substrate formed with a polishing target film by a polishing head; and polishing the polishing target film while restricting movement in a radial direction of the semiconductor substrate by a retainer formed on the polishing head with a tilted surface formed on an inner peripheral section of the retainer, wherein when the polishing target film is polished, an outer peripheral surface of the semiconductor substrate comes into contact with the tilted surface formed on the inner peripheral section of the retainer.

Abstract: A pedestal pad (workpiece supporting table pad) is arranged on the top of a pedestal (workpiece supporting table) for temporarily placing and holding a pre-polished or post-polished wafer (workpiece). This pedestal pad is formed of resin, and at least a surface of the pedestal pad which comes into contact with the wafer is non-absorbable to a fluid. The tissue of the pedestal pad is dense and smooth, and does not have any cavity, such as fine holes, which holds the fluid.

Abstract: A method of fabricating a semiconductor device includes a polishing process of a substrate, wherein the polishing process includes the steps of applying a chemical mechanical polishing process to the substrate on a polishing pad while using slurry, and conditions a surface of the polishing pad, the conditioning step including the step of grinding the surface of said polishing pad by at least first and second conditioning disks of respective, different surface states.

Abstract: A method for fabricating a semiconductor device includes (a) depositing an insulating film on a semiconductor substrate; (b) forming a recess in the insulating film; (c) depositing a conductive film on the insulating film while filling the recess with the conductive film; and (d) polishing the conductive film. Step (d) includes a first polishing substep of using a first polisher pad conditioned with a first dresser and a second polishing substep of using a second polisher pad conditioned with a second dresser different from the first dresser.

Abstract: A method for manufacturing a semiconductor device, including depositing an interconnect material including Cu or Cu alloy over an insulating film, and polishing the interconnect material by CMP with a polishing liquid, wherein the oxidation-reduction potential (ORP) of the polishing liquid is controlled so as to be in the range of 400 mV to 700 mV vs. Ag/AgCl.

Abstract: A method of fabricating a semiconductor device includes a polishing process of a substrate, wherein the polishing process includes the steps of applying a chemical mechanical polishing process to the substrate on a polishing pad while using slurry, and conditions a surface of the polishing pad, the conditioning step including the step of grinding the surface of said polishing pad by at least first and second conditioning disks of respective, different surface states.

Abstract: An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench. Chemical mechanical polishing is executed to expose the insulating surface of the substrate and leave a portion of the conductive film in the trench. The surface of the substrate having the exposed conductive film in the trench and the exposed insulating surface is exposed to first liquid. After being exposed to the first liquid, the surface of the substrate is exposed to second liquid. The first liquid is either solution which contains at least one first substance selected from a first group consisting of benzotriazole, derivative of benzotriazole and interfacial active agent, or water. The second solution is solution which contains the first substance at a density higher than a density of the first liquid.

Abstract: A method of fabricating a semiconductor device includes a polishing process of a substrate, wherein the polishing process includes the steps of applying a chemical mechanical polishing process to the substrate on a polishing pad while using slurry, and conditions a surface of the polishing pad, the conditioning step including the step of grinding the surface of said polishing pad by at least first and second conditioning disks of respective, different surface states.

Abstract: An electric conductive film is formed on the insulating surface of a substrate, the substrate having a trench formed on the insulating surface, and the conductive film being filled in the trench. Chemical mechanical polishing is executed to expose the insulating surface of the substrate and leave a portion of the conductive film in the trench. The surface of the substrate having the exposed conductive film in the trench and the exposed insulating surface is exposed to first liquid. After being exposed to the first liquid, the surface of the substrate is exposed to second liquid. The first liquid is either solution which contains at least one first substance selected from a first group consisting of benzotriazole, derivative of benzotriazole and interfacial active agent, or water. The second solution is solution which contains the first substance at a density higher than a density of the first liquid.

Abstract: A pedestal pad (workpiece supporting table pad) is arranged on the top of a pedestal (workpiece supporting table) for temporarily placing and holding a pre-polished or post-polished wafer (workpiece). This pedestal pad is formed of resin, and at least a surface of the pedestal pad which comes into contact with the wafer is non-absorbable to a fluid. The tissue of the pedestal pad is dense and smooth, and does not have any cavity, such as fine holes, which holds the fluid.

Abstract: A pedestal pad (workpiece supporting table pad) is arranged on the top of a pedestal (workpiece supporting table) for temporarily placing and holding a pre-polished or post-polished wafer (workpiece). This pedestal pad is formed of resin, and at least a surface of the pedestal pad which comes into contact with the wafer is non-absorbable to a fluid. The tissue of the pedestal pad is dense and smooth, and does not have any cavity, such as fine holes, which holds the fluid.

Abstract: A pedestal pad (workpiece supporting table pad) is arranged on the top of a pedestal (workpiece supporting table) for temporarily placing and holding a pre-polished or post-polished wafer (workpiece). This pedestal pad is formed of resin, and at least a surface of the pedestal pad which comes into contact with the wafer is non-absorbable to a fluid. The tissue of the pedestal pad is dense and smooth, and does not have any cavity, such as fine holes, which holds the fluid.

Abstract: A method of fabricating a semiconductor device includes a polishing process of a substrate, wherein the polishing process includes the steps of applying a chemical mechanical polishing process to the substrate on a polishing pad while using slurry, and conditions a surface of the polishing pad, the conditioning step including the step of grinding the surface of said polishing pad by at least first and second conditioning disks of respective, different surface states.