Abstract: A trace data compression system includes a data acquisition circuit which is configured to acquire address information for identifying an address for reading or writing operation of a microcomputer which performs predetermined processing, and data information as operand data stored in the address; an address information compression circuit which is configured to compress the address information having been acquired by the data acquisition circuit and output the address information as compressed; a data information compression circuit which is configured to compress the data information having been acquired by the data acquisition circuit and output the data information as compressed; a data output circuit which is configured to output variable length data containing the address information having been compressed and outputted by the address information compression circuit and the data information having been compressed and outputted by the data information compression circuit.

Abstract: A trace data compression system includes a data acquisition circuit which is configured to acquire address information for identifying an address for reading or writing operation of a microcomputer which performs predetermined processing, and data information as operand data stored in the address; an address information compression circuit which is configured to compress the address information having been acquired by the data acquisition circuit and output the address information as compressed; a data information compression circuit which is configured to compress the data information having been acquired by the data acquisition circuit and output the data information as compressed; a data output circuit which is configured to output variable length data containing the address information having been compressed and outputted by the address information compression circuit and the data information having been compressed and outputted by the data information compression circuit.

Abstract: An information processing system which makes it possible to protect information stored in the ROM of the system from unauthorized access by means of a debug tool. The information processing system includes a ROM for storing an unlocking program and a user program; a CPU for executing said unlocking program and said user program stored in said ROM; an on-chip debug circuit serving to output debug information of said user program as executed by said information processing system; and a debug function disabling circuit serving to disable debug functions of said on-chip debug circuit at power up and to enable the debug functions of said on-chip debug circuit when said unlocking program has been executed.

Abstract: A debugger program product is described which comprises a computer readable medium having computer program logic stored therein for debugging the operation of a target system which is provided with a microprocessor. The debugger program product including a framework module configured such that it can be dynamically linked to a function module which serves to provide a debug function for use in debugging the operation of the target system and can be connected to a simulator capable of performing the simulation of the target system in order to debug the operation of the target system by the use of the debug function of the function module.