Patents by Inventor Tetsuya Tarui

Tetsuya Tarui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10175518
    Abstract: There are provided a display device including a highly reliable wiring having excellent adhesion to an insulating film, and a method for manufacturing the same. A molybdenum-niobium layer has good adhesion to an insulating film, and thus, a first wiring having the molybdenum-niobium layer as an upper layer wiring is tightly adhered to a gate insulating film which is formed on the surface of the upper layer wiring. When there is a need to exchange a semiconductor chip mounted on a connection terminal that is provided at an end portion of a wiring such as a gate lead line or a source lead line formed of the first wiring, an ACF which was used for pressure-bonding of the semiconductor chip remains on the connection terminal even if the semiconductor chip is peeled off.
    Type: Grant
    Filed: July 23, 2015
    Date of Patent: January 8, 2019
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hidenobu Kimoto, Tetsuya Tarui, Yoshihiro Seguchi, Takehisa Sugimoto
  • Patent number: 9927658
    Abstract: An active matrix substrate for a liquid crystal panel of an FFS mode includes a plurality of connecting units in a connecting region in order to electrically connect a common electrode, a first common main wiring 31, and a second common main wiring 32. The connecting unit includes a contact hole 41 that connects a connecting electrode 37 and the first common main wiring 31, the connecting electrode 37 formed integrally with the common electrode, and a contact hole 42 that connects the connecting electrode 37 and the second common main wiring 32. An amorphous Si film 122 of the second common main wiring 32 is formed larger than a main conductor part 131 of the second common main wiring 32 in a position of the contact hole 41, and is covered with SiNx films 151, 152 that are protective insulating films. This prevents the connecting electrode from having a step disconnection at a pattern end of the common main wiring.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: March 27, 2018
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Takehiko Kawamura, Tetsuya Tarui, Hidenobu Kimoto
  • Patent number: 9869917
    Abstract: An active matrix substrate in a liquid crystal panel of an FFS mode has a data line 24 including an amorphous Si film 122, an n+amorphous Si film 123, a main conductor part 133, and an IZO film 141. The main conductor part 133 and the IZO film 141 are etched at a portion close to the end of a covered region of a photoresist 142, to form the n+amorphous Si film 123 larger than the main conductor part 133 and the IZO film 141. A pattern of a photomask for a source layer is made larger than a pattern of a photomask for a pixel electrode layer, to form the amorphous Si film 122 larger than the n+amorphous Si film 123. The main conductor part 133 is formed of a molybdenum-based material, and in a layer over the data line 24, two-layered protective insulating films are formed such that a compressive stress is generated in one film and a tensile stress is generated in the other film. Accordingly, a high-yield active matrix substrate having a common electrode is provided.
    Type: Grant
    Filed: June 24, 2015
    Date of Patent: January 16, 2018
    Assignee: SHARP KABUSHIKI KAISHA
    Inventors: Hidenobu Kimoto, Tetsuya Tarui, Yoshihiro Seguchi, Takehisa Sugimoto
  • Publication number: 20170227799
    Abstract: An active matrix substrate for a liquid crystal panel of an FFS mode includes a plurality of connecting units in a connecting region in order to electrically connect a common electrode, a first common main wiring 31, and a second common main wiring 32. The connecting unit includes a contact hole 41 that connects a connecting electrode 37 and the first common main wiring 31, the connecting electrode 37 formed integrally with the common electrode, and a contact hole 42 that connects the connecting electrode 37 and the second common main wiring 32. An amorphous Si film 122 of the second common main wiring 32 is formed larger than a main conductor part 131 of the second common main wiring 32 in a position of the contact hole 41, and is covered with SiNx films 151, 152 that are protective insulating films. This prevents the connecting electrode from having a step disconnection at a pattern end of the common main wiring.
    Type: Application
    Filed: June 24, 2015
    Publication date: August 10, 2017
    Inventors: Takehiko KAWAMURA, Tetsuya TARUI, Hidenobu KIMOTO
  • Publication number: 20170139296
    Abstract: A first wiring of the present invention is a wiring having a two-layer structure including a lower layer wiring and an upper layer wiring which is formed to cover an upper surface and both side surfaces of the lower layer wiring, and thus, even if the lower layer wiring includes a part where the line width is reduced and which is nearly disconnected due to a particle or the like attached at the time of formation of the lower layer wiring, the probability is extremely low that a particle is attached again, to the upper layer wiring at the time of formation of the upper layer wiring, at a position corresponding to the nearly disconnected part of the lower layer wiring. Moreover, the lower layer wiring and the upper layer wiring are electrically connected to each other.
    Type: Application
    Filed: July 23, 2015
    Publication date: May 18, 2017
    Inventors: Hidenobu KIMOTO, Tetsuya TARUI, Yoshihiro SEGUCHI, Takehisa SUGIMOTO
  • Publication number: 20170139298
    Abstract: An active matrix substrate in a liquid crystal panel of an FFS mode has a data line 24 including an amorphous Si film 122, an n+amorphous Si film 123, a main conductor part 133, and an IZO film 141. The main conductor part 133 and the IZO film 141 are etched at a portion close to the end of a covered region of a photoresist 142, to form the n+amorphous Si film 123 larger than the main conductor part 133 and the IZO film 141. A pattern of a photomask for a source layer is made larger than a pattern of a photomask for a pixel electrode layer, to form the amorphous Si film 122 larger than the n+amorphous Si film 123. The main conductor part 133 is formed of a molybdenum-based material, and in a layer over the data line 24, two-layered protective insulating films are formed such that a compressive stress is generated in one film and a tensile stress is generated in the other film. Accordingly, a high-yield active matrix substrate having a common electrode is provided.
    Type: Application
    Filed: June 24, 2015
    Publication date: May 18, 2017
    Inventors: Hidenobu KIMOTO, Tetsuya TARUI, Yoshihiro SEGUCHI, Takehisa SUGIMOTO
  • Publication number: 20170139260
    Abstract: There are provided a display device including a highly reliable wiring having excellent adhesion to an insulating film, and a method for manufacturing the same. A molybdenum-niobium layer has good adhesion to an insulating film, and thus, a first wiring having the molybdenum-niobium layer as an upper layer wiring is tightly adhered to a gate insulating film which is formed on the surface of the upper layer wiring. When there is a need to exchange a semiconductor chip mounted on a connection terminal that is provided at an end portion of a wiring such as a gate lead line or a source lead line formed of the first wiring, an ACF which was used for pressure-bonding of the semiconductor chip remains on the connection terminal even if the semiconductor chip is peeled off.
    Type: Application
    Filed: July 23, 2015
    Publication date: May 18, 2017
    Inventors: Hidenobu KIMOTO, Tetsuya TARUI, Yoshihiro SEGUCHI, Takehisa SUGIMOTO
  • Patent number: 6590629
    Abstract: A liquid crystal display including an active matrix substrate furnished with a matrix of TFTs, in which a plurality of TAB substrates each having a driver IC are connected to the active matrix substrate through an ACF, and the driver ICs are connected to source bus lines through the ACF. Also, adjacent driver ICs disposed on the mounting substrates are connected to each other through common connection lines formed on the active matrix substrate. Consequently, the size and weight of the mounting substrates used to provide the driver ICs and lines connected to the same can be reduced, thereby making it possible to provide a light and inexpensive liquid crystal display having a small frame edge portion.
    Type: Grant
    Filed: February 4, 2000
    Date of Patent: July 8, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Toshihiko Hirobe, Tetsuya Tarui, Yoshitaka Hibino, Naofumi Kondo
  • Patent number: 6529251
    Abstract: A liquid crystal display device includes: a source electrode (gate electrode) having an Al or Al alloy layer; a pixel electrode provided above the source electrode (gate electrode); and interlayer insulator films interposed between the source electrode (gate electrode) and the pixel electrode by depositing a TFT protection film as an inorganic insulator film and an organic insulator film in this sequence when viewed from the source electrode, so as to cover the source electrode (gate electrode).
    Type: Grant
    Filed: February 17, 2000
    Date of Patent: March 4, 2003
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Yoshitaka Hibino, Tetsuya Tarui, Toshihiko Hirobe
  • Publication number: 20020126243
    Abstract: A liquid crystal display device includes: a source electrode (gate electrode) having an Al or Al alloy layer; a pixel electrode provided above the source electrode (gate electrode); and interlayer insulator films interposed between the source electrode (gate electrode) and the pixel electrode by depositing a TFT protection film as an inorganic insulator film and an organic insulator film in this sequence when viewed from the source electrode, so as to cover the source electrode (gate electrode).
    Type: Application
    Filed: February 17, 2000
    Publication date: September 12, 2002
    Inventors: Yoshitaka Hibino, Tetsuya Tarui, Toshihiko Hirobe
  • Patent number: 5657553
    Abstract: A substrate drying apparatus comprises a treatment vessel for containing IPA in the form of liquid, an IPA source for supplying IPA into the treatment vessel, a first heat exchanger which is equipped with a heat exchanger tube dipped in IPA and allowing steam to pass therein, the first heat exchanger allowing the steam and IPA to perform heat exchange therebetween to thereby evaporate IPA, and a second heat exchanger provided on or above an upper portion of the treatment vessel and equipped with a heat exchanger tube for allowing a coolant to pass therein, the second heat exchanger allowing the coolant and the evaporated IPA to perform heat exchange therebetween to thereby condense the evaporated IPA.
    Type: Grant
    Filed: November 28, 1995
    Date of Patent: August 19, 1997
    Assignees: Sharp Kabushiki Kaisha, Kimmon Quartz Co., Ltd.
    Inventors: Tetsuya Tarui, Hiromitsu Asano, Hajime Onoda