Patents by Inventor Tetsuya Tsukihara

Tetsuya Tsukihara has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8338908
    Abstract: According to one embodiment, a semiconductor device includes: a substrate in which, on a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type and a semiconductor layer of the second conductivity type are stacked; trench that define an element forming region in the substrate; element isolation insulation film formed in the trench; and a semiconductor element formed in the element forming region. The trench include first trench formed from the surface of the substrate to boundary depth and second trench formed from the boundary depth to the bottom and having a diameter smaller than that of the first trench. First diffusion layers connected to the buried layer are formed around the first or second trench according to inter-element breakdown voltage required of the semiconductor element.
    Type: Grant
    Filed: August 24, 2010
    Date of Patent: December 25, 2012
    Assignee: Kabushiki Kaisha Toshiba
    Inventor: Tetsuya Tsukihara
  • Publication number: 20110073944
    Abstract: According to one embodiment, a semiconductor device includes: a substrate in which, on a semiconductor substrate of a first conductivity type, a buried layer of a second conductivity type and a semiconductor layer of the second conductivity type are stacked; trench that define an element forming region in the substrate; element isolation insulation film formed in the trench; and a semiconductor element formed in the element forming region. The trench include first trench formed from the surface of the substrate to boundary depth and second trench formed from the boundary depth to the bottom and having a diameter smaller than that of the first trench. First diffusion layers connected to the buried layer are formed around the first or second trench according to inter-element breakdown voltage required of the semiconductor element.
    Type: Application
    Filed: August 24, 2010
    Publication date: March 31, 2011
    Applicant: KABUSHIKI KAISHA TOSHIBA
    Inventor: Tetsuya Tsukihara
  • Patent number: 5605488
    Abstract: A plurality of cells are provided in a concave portion of a top plate. A cloth to which water is penetrated is provided in a back face of each cell, and a wafer is attracted by the cloth. First and second pipes are connected to each cell. The first pipe introduces liquid to the cell, and the second pipe discharges liquid from the cell, and guides liquid to the first pipe. A constant-temperature device is provided to each first pipe, and a temperature of liquid of each cell is adjusted by the constant-temperature device in accordance with a temperature distribution of the wafer. Whereby, a polishing rate of each part of the wafer can be equalized.
    Type: Grant
    Filed: October 27, 1994
    Date of Patent: February 25, 1997
    Assignee: Kabushiki Kaisha Toshiba
    Inventors: Hiroyuki Ohashi, Naoto Miyashita, Ichiro Katakabe, Tetsuya Tsukihara