Abstract: An electronic component comprises a substrate including a main surface on which a functional unit is formed and a cap layer defining a cavity enclosing and covering the functional unit. The cap layer is provided with holes communicating an inside of the cavity with an outside of the cavity. A resin layer covers the cap layer and the main surface and includes one or more bores and a solder layer having a thickness less than a thickness of the resin layer disposed within the one or more bores.

Abstract: A method of manufacturing an electronic device includes preparing an electronic component including a first substrate on a main surface of which a functional unit and a first resin layer are formed. The first resin layer has a first surface facing the main surface of the first substrate, a second surface opposed to the first surface, a cavity on the first surface enclosing the functional unit, and a portion defining a wall of the cavity. The first resin layer defines a recess provided with a solder layer on the second surface. The method further includes preparing a second substrate having an electrode pad formed on a main surface, aligning the electronic component with the second substrate to layer the solder layer and the electrode pad in contact with the solder layer, and forming the electronic component and the second substrate into the electronic device.

Abstract: An electronic component comprises a substrate including a main surface on which a functional unit is formed and a cap layer defining a cavity enclosing and covering the functional unit. The cap layer is provided with holes communicating an inside of the cavity with an outside of the cavity. A resin layer covers the cap layer and the main surface and includes one or more bores and a solder layer having a thickness less than a thickness of the resin layer disposed within the one or more bores.

Abstract: A method of fabricating an electronic component includes forming a functional unit on a main surface of a substrate, forming a sacrificial layer covering the functional unit on the main surface, forming a cap layer covering the sacrificial layer, the cap layer forming a periphery enclosing the cavity on the main surface, forming holes through the cap layer, forming a cavity by removing the sacrificial layer using a wet etching process through the holes, the holes including a peripheral hole communicating an inside of the cavity with an outside of the cavity along the main surface, and forming a first resin layer covering the cap layer and the main surface.

Abstract: A method of manufacturing an electronic device includes preparing an electronic component including a first substrate on a main surface of which a functional unit and a first resin layer are formed. The first resin layer has a first surface facing the main surface of the first substrate, a second surface opposed to the first surface, a cavity on the first surface enclosing the functional unit, and a portion defining a wall of the cavity. The first resin layer defines a recess provided with a solder layer on the second surface. The method further includes preparing a second substrate having an electrode pad formed on a main surface, aligning the electronic component with the second substrate to layer the solder layer and the electrode pad in contact with the solder layer, and forming the electronic component and the second substrate into the electronic device.

Abstract: An electronic component may include a substrate having a functional unit formed on a main surface of the substrate and a first resin layer formed on the main surface, the first resin layer having a first surface facing the main surface and a second surface opposed to the first surface, the first resin layer defining a cavity on the first surface enclosing the functional unit, the first resin layer defining a recess on the second surface, and a solder layer being formed in the recess so as not to exceed the second surface in a thickness direction. The functional unit may include a surface acoustic wave (SAW) element or a film bulk acoustic resonator (FBAR) having a mechanically movable portion. The substrate may be formed of dielectric material.

Abstract: An electronic component may include a substrate having a functional unit formed on a main surface of the substrate and a first resin layer formed on the main surface, the first resin layer having a first surface facing the main surface and a second surface opposed to the first surface, the first resin layer defining a cavity on the first surface enclosing the functional unit, the first resin layer defining a recess on the second surface, and a solder layer being formed in the recess so as not to exceed the second surface in a thickness direction. The functional unit may include a surface acoustic wave (SAW) element or a film bulk acoustic resonator (FBAR) having a mechanically movable portion. The substrate may be formed of dielectric material.

Abstract: A method of fabricating an electronic component includes forming a functional unit on a main surface of a substrate, forming a sacrificial layer covering the functional unit on the main surface, forming a cap layer covering the sacrificial layer, the cap layer forming a periphery enclosing the cavity on the main surface, forming holes through the cap layer, forming a cavity by removing the sacrificial layer using a wet etching process through the holes, the holes including a peripheral hole communicating an inside of the cavity with an outside of the cavity along the main surface, and forming a first resin layer covering the cap layer and the main surface.

Abstract: A high positional accuracy of a semiconductor chip is attained to stabilize the quality of a semiconductor device. In a die bonding process during assembly of an SIP, a microcomputer chip not required to have a high positional accuracy is picked up with a surface non-contact type collet and is die-bonded onto a first chip mounting portion, thereafter, an ASIC chip required to have a high positional accuracy is picked up with a surface contact type collet and die-bonded onto a second chip mounting portion. By thus using two types of collets properly, not only a high positional accuracy of the ASIC chip which has been die-bonded with the surface contact type collet is attained, but also the quality of the SIP is stabilized.

Abstract: A high positional accuracy of a semiconductor chip is attained to stabilize the quality of a semiconductor device. In a die bonding process during assembly of an SIP, a microcomputer chip not required to have a high positional accuracy is picked up with a surface non-contact type collet and is die-bonded onto a first chip mounting portion, thereafter, an ASIC chip required to have a high positional accuracy is picked up with a surface contact type collet and die-bonded onto a second chip mounting portion. By thus using two types of collets properly, not only a high positional accuracy of the ASIC chip which has been die-bonded with the surface contact type collet is attained, but also the quality of the SIP is stabilized.

Abstract: A semiconductor chip, substrate employing plural bonding steps to ensure complete bonding particularly of peripheral edges. Embodiments include placing an adhesive layer on a chip mounting substrate positioned on a first supporting device, pressing a semiconductor chip against the chip mounting substrate to bond the semiconductor chip temporarily to the chip mounting substrate temporarily bonded chip on a second supporting device, and applying chip to straighten warpage and to bond the chip entirely to the chip mounting substrate.

Abstract: In a semiconductor device fabricating method, a plurality of wafers each having a plurality of chips into is carried and is placed in a die bonder. Chips taken out from the plurality of wafers is bonded together, respectively, and superpose in a stack by bonding layers to form a chip assembly. The chip assembly to a die pad by a bonding layer is bonded. Thus, the die bonder is able to bond the chip assembly consisting of the plurality of chips to the die pad, so that the process time of a die bonding process for bonding the plurality of chips to the die pad is comparatively short, the semiconductor fabricating apparatus produces semiconductor devices at an improved productivity, has a comparatively small scale and needs a comparatively low equipment investment.

Abstract: A semiconductor device and a manufacturing method thereof are provided with downsizing and densification achieved by reducing the thickness of the semiconductor device without increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed to overlap in the range of height with the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, a wire connects the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wire. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.

Abstract: A section of predetermined geometry and area is provided on or in a die pad of a lead frame and taken as a mark to be used for checking the position of a semiconductor chip. If the semiconductor chip is placed outside an allowable range in the X direction, the semiconductor chip overlaps the mark, thereby changing the geometry of an observable portion (slanted portion) of the mark. By means of the change, a positional deviation of the semiconductor chip in the X direction can be ascertained. A positional deviation of the semiconductor chip in Y direction is determined, by observing whether or not an electrode is situated between extensions of sides of a certain portion of the section.

Abstract: A semiconductor device and a manufacturing method thereof are provided with downsizing and densification achieved by reducing the thickness of the semiconductor device without increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed to overlap in the range of height with the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, a wire connects the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wire. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.

Abstract: In a semiconductor device fabricating method, a plurality of wafers each having a plurality of chips into is carried and is placed in a die bonder. Chips taken out from the plurality of wafers is bonded together, respectively, and superpose in a stack by bonding layers to form a chip assembly. The chip assembly to a die pad by a bonding layer is bonded. Thus, the die bonder is able to bond the chip assembly consisting of the plurality of chips to the die pad, so that the process time of a die bonding process for bonding the plurality of chips to the die pad is comparatively short, the semiconductor fabricating apparatus produces semiconductor devices at an improved productivity, has a comparatively small scale and needs a comparatively low equipment investment.

Abstract: In a semiconductor device fabricating method, a plurality of wafers each having a plurality of chips into is carried and is placed in a die bonder. Chips taken out from the plurality of wafers is bonded together, respectively, and superpose in a stack by bonding layers to form a chip assembly. The chip assembly to a die pad by a bonding layer is bonded. Thus, the die bonder is able to bond the chip assembly consisting of the plurality of chips to the die pad, so that the process time of a die bonding process for bonding the plurality of chips to the die pad is comparatively short, the semiconductor fabricating apparatus produces semiconductor devices at an improved productivity, has a comparatively small scale and needs a comparatively low equipment investment.

Abstract: A semiconductor device and a manufacturing method for downsizing and densification achieved by reducing the thickness of the semiconductor device without an increase in area. Terminal electrodes are arranged, in plan view, outside a region where semiconductor chips are arranged. A lower semiconductor chip is placed overlapping in height the terminal electrodes, an upper semiconductor chip is placed above the lower semiconductor chip, wires connect the upper and lower semiconductor chips to the terminal electrodes, and an encapsulating resin encapsulates the upper and lower semiconductor chips and wires. The encapsulating resin has its bottom surface coplanar with the bottom surface of the terminal electrodes.

Abstract: A section of predetermined geometry and area is provided on or in a die pad of a lead frame and taken as a mark to be used for checking the position of a semiconductor chip. If the semiconductor chip is placed outside an allowable range in the X direction, the semiconductor chip overlaps the mark, thereby changing the geometry of an observable portion (slanted portion) of the mark. By means of the change, a positional deviation of the semiconductor chip in the X direction can be ascertained. A positional deviation of the semiconductor chip in Y direction is determined, by observing whether or not an electrode is situated between extensions of sides of a certain portion of the section.

Abstract: A semiconductor chip mounting substrate provided with an adhesive layer is placed on a first supporting device included in a chip bonding unit. A collet holds a semiconductor chip, carries the same to the semiconductor chip mounting substrate placed on the first supporting device and presses the same against the semiconductor chip mounting substrate to bond the semiconductor chip temporarily to the semiconductor chip mounting substrate. The semiconductor chip mounting substrate to which the semiconductor chip is bonded temporarily is placed on a second supporting device included in a chip pressing unit. A pressing device applies pressure to the semiconductor chip to straighten the warped semiconductor chip and to bond the same entirely to the semiconductor chip mounting substrate.