Abstract: The delay time for the transfer of data signals between pluralities of logic circuits is automatically regulated to be in a desired range. In order to regulate the delay time of the data signal transfer, a common standard signal SYNC is distributed to the logic circuits from a standard signal generator source. In the sending side of one logic circuit, the standard signal is applied through a selector circuit to a flip-flop circuit and then transferred to the receiving side of another logic circuit. Specifically, the transferred standard signal passes through a variable delay circuit to a flip flop circuit on the receiving side of the other logic circuit where it is compared with the standard signal received from the standard signal generator source, which has passed through a delay circuit of a standard delay value. The result of the comparison is used to adjust the variable delay circuit that controls the delay time for the transferred standard signal.

Abstract: This invention relates to a copper alloy for reliable electrical connection comprising 0.5-3.0 wt% of Co, 0.03-0.4 wt% of P and the balance being composed of Cu and impurities thereof, which is characterized by that it excels in connecting characteristics relative to connection by compression and particularly does not permit a glow discharge and growth of cuprous oxide.

Abstract: This invention relates to a copper alloy for reliable electrical connection comprising 0.5-3.0 wt% of Fe, 0.3-0.8 wt% of Zn and the balance being composed of Cu and impurities thereof, which is characterized by that it excels in connecting characteristics relative to connection by compression and, particularly does not permit a glow discharge and growth of cuprous oxide.