Patents by Inventor Tetsuya Yasuda
Tetsuya Yasuda has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 12254198Abstract: According to one embodiment, a memory system includes a non-volatile memory including a plurality of physical blocks and a controller. The controller is configured to allocate the plurality of physical blocks to a plurality of first block sets each including physical blocks among the plurality of physical blocks, generate a plurality of groups obtained by grouping the plurality of first block sets by the number of defective physical blocks included in each of the plurality of first block sets, and select a plurality of the first block sets from at least two groups of the plurality of groups to generate a second block set from the plurality of selected first block sets.Type: GrantFiled: February 27, 2023Date of Patent: March 18, 2025Assignee: Kioxia CorporationInventor: Tetsuya Yasuda
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Patent number: 12217723Abstract: The invention of the present application realizes image display that when multiple display screens are being used, properly controls the luminance of one display screen on the basis of the luminance of another display screen. An image display system for displaying images in display areas is provided. The image display system includes a first display area, a second display area, and a luminance determination unit. The luminance determination unit is configured to determine luminance of the second display area on the basis of luminance of the first display area and positional relationships between the first display area, the second display area, and a user and to display the second display area at the determined luminance.Type: GrantFiled: February 9, 2022Date of Patent: February 4, 2025Assignee: EIZO CorporationInventors: Tetsuya Yasuda, Airi Kurokawa, Masahiro Sugumi
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Publication number: 20240411472Abstract: An example memory system includes a non-volatile memory and a controller. The controller is communicatively coupled with a host and configured to control the non-volatile memory. The controller is configured to receive, from the host, first information about mapping of data of a file to a logical address space of the memory system, and relocate, in a physical address space of the non-volatile memory, the data of the file that is fragmented in the physical address space so that the data of the file is continuous in the physical address space based on the received first information, and also on second information in which a correspondence relationship between a logical address indicating a position in the logical address space and a physical address indicating a position in the physical address space is recorded.Type: ApplicationFiled: June 7, 2024Publication date: December 12, 2024Applicant: Kioxia CorporationInventor: Tetsuya YASUDA
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Publication number: 20240312434Abstract: [Problem] The invention of the present application realizes image display that when multiple display screens are being used, properly controls the luminance of one display screen on the basis of the luminance of another display screen. [Solving Means] An image display system for displaying images in display areas is provided. The image display system includes a first display area, a second display area, and a luminance determination unit. The luminance determination unit is configured to determine luminance of the second display area on the basis of luminance of the first display area and positional relationships between the first display area, the second display area, and a user and to display the second display area at the determined luminance.Type: ApplicationFiled: February 9, 2022Publication date: September 19, 2024Applicant: EIZO CorporationInventors: Tetsuya YASUDA, Airi KUROKAWA, Masahiro SUGUMI
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Patent number: 11803320Abstract: A controller of a memory system according to an embodiment manages, for each of a plurality of blocks, first information indicating whether a corresponding block is in use which indicates a state where the data is stored, second information indicating the number of erasures, and third information indicating a waiting time until next erasure. The controller executes first sequential write received from a host, and determines whether to execute processing of leveling the number of erasures for each of the plurality of blocks based on a first difference, a second difference, and a third difference when executing second sequential write received from the host.Type: GrantFiled: December 10, 2021Date of Patent: October 31, 2023Assignee: Kioxia CorporationInventor: Tetsuya Yasuda
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Publication number: 20230315310Abstract: According to one embodiment, a memory system includes a non-volatile memory including a plurality of physical blocks and a controller. The controller is configured to allocate the plurality of physical blocks to a plurality of first block sets each including physical blocks among the plurality of physical blocks, generate a plurality of groups obtained by grouping the plurality of first block sets by the number of defective physical blocks included in each of the plurality of first block sets, and select a plurality of the first block sets from at least two groups of the plurality of groups to generate a second block set from the plurality of selected first block sets.Type: ApplicationFiled: February 27, 2023Publication date: October 5, 2023Applicant: Kioxia CorporationInventor: Tetsuya YASUDA
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Patent number: 11763777Abstract: An image display device, image display system, image display method and computer program which are configured so that not only the gradation characteristic at the luminance over 0.05 (cd/m2) but also the gradation characteristic at the luminance less than 0.05 (cd/m2) satisfies the DICOM. The image display device includes an image display unit; and an image processing unit. The image processing unit is configured to display the image data on the image display unit based on first and second gradation characteristics, a luminance of the first gradation characteristic is 0.05 (cd/m2) or more, a luminance of the second gradation characteristic is less than 0.05 (cd/m2), the first gradation characteristic complies with GSDF (Grayscale Standard Display Function) gradation characteristic of DICOM standard, and the first and second gradation characteristics are defined to satisfy a relationship between a JND value and a corresponding luminance.Type: GrantFiled: May 23, 2019Date of Patent: September 19, 2023Assignee: EIZO CorporationInventor: Tetsuya Yasuda
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Patent number: 11645003Abstract: According to one embodiment, a memory system includes a non-volatile memory, and a controller configured to control the non-volatile memory. The controller is configured to write data to the non-volatile memory, read the written data from the non-volatile memory after writing of the data is completed, generate parity data corresponding to the read data, and write the generated parity data to a memory for parity storage.Type: GrantFiled: June 15, 2021Date of Patent: May 9, 2023Assignee: Kioxia CorporationInventors: Atsushi Okamoto, Tetsuya Yasuda, Akinori Nagaoka
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Publication number: 20230087002Abstract: A controller of a memory system according to an embodiment manages, for each of a plurality of blocks, first information indicating whether a corresponding block is in use which indicates a state where the data is stored, second information indicating the number of erasures, and third information indicating a waiting time until next erasure. The controller executes first sequential write received from a host, and determines whether to execute processing of leveling the number of erasures for each of the plurality of blocks based on a first difference, a second difference, and a third difference when executing second sequential write received from the host.Type: ApplicationFiled: December 10, 2021Publication date: March 23, 2023Applicant: Kioxia CorporationInventor: Tetsuya YASUDA
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Publication number: 20220300189Abstract: According to one embodiment, a memory system includes a non-volatile memory, and a controller configured to control the non-volatile memory. The controller is configured to write data to the non-volatile memory, read the written data from the non-volatile memory after writing of the data is completed, generate parity data corresponding to the read data, and write the generated party data to a memory for parity storage.Type: ApplicationFiled: June 15, 2021Publication date: September 22, 2022Inventors: Atsushi Okamoto, Tetsuya Yasuda, Akinori Nagaoka
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Publication number: 20220215814Abstract: An image display device, image display system, image display method and computer program which are configured so that not only the gradation characteristic at the luminance over 0.05 (cd/m2) but also the gradation characteristic at the luminance less than 0.05 (cd/m2) satisfies the DICOM. The image display device includes an image display unit; and an image processing unit. The image processing unit is configured to display the image data on the image display unit based on first and second gradation characteristics, a luminance of the first gradation characteristic is 0.05 (cd/m2) or more, a luminance of the second gradation characteristic is less than 0.05 (cd/m2), the first gradation characteristic complies with GSDF (Grayscale Standard Display Function) gradation characteristic of DICOM standard, and the first and second gradation characteristics are defined to satisfy a relationship between a JND value and a corresponding luminance.Type: ApplicationFiled: May 23, 2019Publication date: July 7, 2022Applicant: EIZO CorporationInventor: Tetsuya YASUDA
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Patent number: 11366751Abstract: A storage device includes a nonvolatile memory with physical blocks each including a plurality of clusters, and a controller that maintains a first table storing a relationship between a logical address and a physical address of the cluster, and a second table storing a relationship between a logical block and physical blocks allocated thereto. The controller performs garbage collection processing which includes copying data read from valid clusters of the first logical block to a destination logical block, creating a new logical block when the data read contains an uncorrectable error, allocating the physical blocks of the first logical block to the new logical block, and updating the second table so that the physical blocks of the first logical block are associated with the new logical block and no physical blocks are associated with the first logical block.Type: GrantFiled: July 21, 2020Date of Patent: June 21, 2022Assignee: KIOXIA CORPORATIONInventor: Tetsuya Yasuda
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Publication number: 20200349070Abstract: A storage device includes a nonvolatile memory with physical blocks each including a plurality of clusters, and a controller that maintains a first table storing a relationship between a logical address and a physical address of the cluster, and a second table storing a relationship between a logical block and physical blocks allocated thereto. The controller performs garbage collection processing which includes copying data read from valid clusters of the first logical block to a destination logical block, creating a new logical block when the data read contains an uncorrectable error, allocating the physical blocks of the first logical block to the new logical block, and updating the second table so that the physical blocks of the first logical block are associated with the new logical block and no physical blocks are associated with the first logical block.Type: ApplicationFiled: July 21, 2020Publication date: November 5, 2020Inventor: Tetsuya YASUDA
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Patent number: 10754771Abstract: A storage device includes a nonvolatile memory with physical blocks each including a plurality of clusters, and a controller that maintains a first table storing a relationship between a logical address and a physical address of the cluster, and a second table storing a relationship between a logical block and physical blocks allocated thereto. The controller performs garbage collection processing which includes copying data read from valid clusters of the first logical block to a destination logical block, erasing all data of the physical blocks of the first logical block, creating a new logical block when the data read contains an uncorrectable error, allocating the physical blocks of the first logical block to the new logical block, updating the second table so that the physical blocks of the first logical block are associated with the new logical block and no physical blocks are associated with the first logical block.Type: GrantFiled: February 25, 2019Date of Patent: August 25, 2020Assignee: Toshiba Memory CorporationInventor: Tetsuya Yasuda
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Publication number: 20200034290Abstract: A storage device includes a nonvolatile memory with physical blocks each including a plurality of clusters, and a controller that maintains a first table storing a relationship between a logical address and a physical address of the cluster, and a second table storing a relationship between a logical block and physical blocks allocated thereto. The controller performs garbage collection processing which includes copying data read from valid clusters of the first logical block to a destination logical block, erasing all data of the physical blocks of the first logical block, creating a new logical block when the data read contains an uncorrectable error, allocating the physical blocks of the first logical block to the new logical block, updating the second table so that the physical blocks of the first logical block are associated with the new logical block and no physical blocks are associated with the first logical block.Type: ApplicationFiled: February 25, 2019Publication date: January 30, 2020Inventor: Tetsuya YASUDA
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Publication number: 20190087299Abstract: According to one embodiment, a memory system is connectable to a host. The memory system includes a nonvolatile first memory, and a controller circuit. The controller circuit controls to transfer data between the host and the first memory. The controller circuit measures a rate of data transfer between the host and the memory system. The controller circuit calculates a first level which is a performance level corresponding to a processing capability of the host, on the basis of the measured rate. The controller circuit operates in a first mode of controlling performance of the data transfer at the first level.Type: ApplicationFiled: February 14, 2018Publication date: March 21, 2019Inventors: Tetsuya Yasuda, Fumio Hara
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Patent number: 8025020Abstract: To provide the auxiliary float of a floating structure which can prolong the lifetime of the floating structure by reducing external force acting on the brace and can be used even at very deep water by increasing buoyancy, and to provide a remodeling method of the floating structure. The auxiliary float (11) comprises two floats (12) coupled, respectively, to lower portions of two lower hulls (1) constituting a floating structure, two main coupling members (13) for coupling the floats (12) to each other, and four sub-coupling members (14) for coupling the main coupling member (13) and the float (12). The auxiliary float (11) is produced in advance and the floating structure is mounted on the auxiliary float (11), and then the lower hull (1) and the float (12) are connected, thus remodeling the floating structure.Type: GrantFiled: July 5, 2007Date of Patent: September 27, 2011Assignee: IHI Marine United Inc.Inventors: Tetsuya Yasuda, Masanori Nemoto, Hiromitsu Yamamoto, Kozo Yokokura
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Publication number: 20090183666Abstract: Problems To provide the auxiliary float of a floating structure which can prolong the lifetime of the floating structure by reducing external force acting on the brace and can be used even at very deep water by increasing buoyancy, and to provide a remodeling method of the floating structure. Means for Solving Problems The auxiliary float (11) comprises two floats (12) coupled, respectively, to lower portions of two lower hulls (1) constituting a floating structure, two main coupling members (13) for coupling the floats (12) to each other, and four sub-coupling members (14) for coupling the main coupling member (13) and the float (12). The auxiliary float (11) is produced in advance and the floating structure is mounted on the auxiliary float (11), and then the lower hull (1) and the float (12) are connected, thus remodeling the floating structure.Type: ApplicationFiled: July 5, 2007Publication date: July 23, 2009Inventors: Tetsuya Yasuda, Masanori Nemoto, Hiromitsu Yamamoto, Kozo Yokokura
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Patent number: 7502038Abstract: A liquid crystal display monitor comprises an LCD panel, a conversion section, an LUT, a monitor communication section, a light source control section, and a light source. The conversion section comprises an LUT. The LUT comprises, for example, an LUT for red, an LUT for green, and an LUT for blue corresponding to the three primary colors of RGB. A PC is connected to the liquid crystal display monitor, while an optical sensor is attached to a display screen of the LCD panel. On the basis of brightness (white brightness and single color brightness) and white chromaticity having been acquired in a state that a white screen is displayed at a plurality of gradations of display input gradation, a conversion table for a plurality of colors (each color of RGB) is calibrated so that display characteristics of a color display unit is calibrated.Type: GrantFiled: October 20, 2004Date of Patent: March 10, 2009Assignee: Eizo Nanao CorporationInventors: Tetsuya Yasuda, Naoaki Hirata
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Publication number: 20070146266Abstract: A liquid crystal display monitor comprises an LCD panel, a conversion section, an LUT, a monitor communication section, a light source control section, and a light source. The conversion section comprises an LUT. The LUT comprises, for example, an LUT for red, an LUT for green, and an LUT for blue corresponding to the three primary colors of RGB. A PC is connected to the liquid crystal display monitor, while an optical sensor is attached to a display screen of the LCD panel. On the basis of brightness (white brightness and single color brightness) and white chromaticity having been acquired in a state that a white screen is displayed at a plurality of gradations of display input gradation, a conversion table for a plurality of colors (each color of RGB) is calibrated so that display characteristics of a color display unit is calibrated.Type: ApplicationFiled: October 20, 2004Publication date: June 28, 2007Inventors: Tetsuya Yasuda, Naoaki Hirata