Patents by Inventor Tetsuya Yasui

Tetsuya Yasui has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060056242
    Abstract: A communication system that can improve communication quality by accurately re-creating reproduction timing at the receiving end even at the time of receiving VBR data or in the case of the occurrence of a packet loss. A send rate recognition section recognizes a send rate from a time stamp. A memory stores data. A dummy data addition section adds dummy data for correcting the difference between a read rate set for reading out data from the memory and the send rate to the data written to the memory. A read clock generation section generates a read clock which is equal to the read rate. A dummy data removal section removes the dummy data from the data read out from the memory on the basis of the read clock.
    Type: Application
    Filed: November 8, 2005
    Publication date: March 16, 2006
    Inventors: Naoyuki Takeshita, Toshikazu Senuki, Tetsuya Yasui, Shinichirou Miyajima, Yuji Ishii, Katsuhiro Eguchi, Masahiro Abe, Jun Endoh
  • Patent number: 6878762
    Abstract: A polyamide resin composition, with a sufficiently high weather resistance even when the polyamide resin contains a pigment containing a metal component such as titanium oxide, or a residual catalyst containing a metal component, is provided by a polyamide resin composition comprising from 0.05 to 2 parts by weight of an N—O—R type low-molecular-weight hindered amine light-resistant stabilizer and a high-molecular-weight hindered amine light-resistant stabilizer per 100 parts by weight as a total of the composition.
    Type: Grant
    Filed: September 20, 2002
    Date of Patent: April 12, 2005
    Assignee: Ube Industries, Ltd.
    Inventors: Yoshihiro Urata, Tetsuya Yasui
  • Patent number: 6782065
    Abstract: An apparatus for reproducing a system clock provided with a reproducing unit for reproducing a first time reference clock T1, a generating unit for generating a system clock Sck, a generating unit for generating a second time reference clock T2, a synchronization control unit for minimizing, based on the clocks T1 and T2, the deviation between these clocks, a first calculating unit for calculating a difference between counts of the clock T1 counted in a predetermined time interval, and a second calculating unit for calculating a difference between counts of the clock T2 counted in a predetermined time interval, the outputs of the calculation of the differences being input to the synchronization control unit to minimize the deviation between the clocks, whereby it becomes possible to reproduce high quality data even when switching channels from one node to another node when reproducing digital data from a plurality of sending side nodes at a receiving side node.
    Type: Grant
    Filed: January 26, 2000
    Date of Patent: August 24, 2004
    Assignee: Fujitsu Limited
    Inventors: Toshihiro Yamanaka, Takehiko Fujiyama, Tetsuya Yasui
  • Publication number: 20030065065
    Abstract: A polyamide resin composition, with a sufficiently high weather resistance even when the polyamide resin contains a pigment containing a metal component such as titanium oxide, or a residual catalyst containing a metal component, is provided by a polyamide resin composition comprising from 0.05 to 2 parts by weight of an N—O—R type low-molecular-weight hindered amine light-resistant stabilizer and a high-molecular-weight hindered amine light-resistant stabilizer per 100 parts by weight as a total of the composition.
    Type: Application
    Filed: September 20, 2002
    Publication date: April 3, 2003
    Applicant: UBE INDUSTRIES, LTD.
    Inventors: Yoshihiro Urata, Tetsuya Yasui
  • Patent number: 6490004
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: December 3, 2002
    Assignee: Fujitsu Limited
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Patent number: 6490003
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: December 3, 2002
    Assignee: Fujitsu Limited
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Patent number: 6483549
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Grant
    Filed: October 23, 2001
    Date of Patent: November 19, 2002
    Assignee: Fujitsu Limited
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Publication number: 20020057377
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Application
    Filed: October 23, 2001
    Publication date: May 16, 2002
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Publication number: 20020057375
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Application
    Filed: October 23, 2001
    Publication date: May 16, 2002
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Publication number: 20020057376
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Application
    Filed: October 23, 2001
    Publication date: May 16, 2002
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui
  • Patent number: 6317163
    Abstract: A video signal processing apparatus includes a receiver receiving an incoming video signal and producing an output video signal in response thereto, a limit setup unit setting up at least one of an upper limit value and a lower limit value for the output video signal, and a limiter supplied with the output video signal from the receiver and further with at least one of the upper limit value and the lower limit value from the limit setup unit, wherein the limiter limits a level of the output video signal produced by the receiver, by comparing the level of the output video signal according to any of the upper limit value and the lower limit value.
    Type: Grant
    Filed: October 30, 1998
    Date of Patent: November 13, 2001
    Assignee: Fujitsu Ltd.
    Inventors: Hideki Miyasaka, Hiroshi Ohtsuru, Tetsuya Yasui