Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.

Abstract: A semiconductor device includes a first transistor and a second transistor. The first transistor includes a first body layer and a first connection part. The second transistor includes a second body layer and a second connection part. A second impedance, which is, in a path between the second connection part and the second body layer, inclusive, a maximum impedance seen by the first source electrode in the second body layer, is greater than a first impedance, which is, in a path between the first connection part and the first body layer, inclusive, a maximum impedance seen by the first source electrode in the first body layer.

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

Abstract: In a semiconductor device in the present disclosure, a first nitride semiconductor layer has a two-dimensional electron gas channel in a vicinity of an interface with a second nitride semiconductor layer. In plan view, an electrode portion is provided between a first electrode and a second electrode with a space between the first electrode and the second electrode, and a space between the second electrode and the electrode portion is smaller than the space between the first electrode and the electrode portion. An energy barrier is provided in a junction surface between the electrode portion and the second nitride semiconductor layer, the energy barrier indicating a rectifying action in a forward direction from the electrode portion to the second nitride semiconductor layer, and a bandgap of the second nitride semiconductor layer is wider than a bandgap of the first nitride semiconductor layer.

Abstract: A converter includes: a bridge diode; an X capacitor provided upstream of the bridge diode; a smoothing capacitor provided downstream of the bridge diode; an AC shutoff detection circuit which outputs an AC shutoff detection signal when input AC voltage is shut off; and a discharging circuit which is connected to a connection point at which the cathode of the bridge diode and the smoothing capacitor are connected, and allows residual charges in the smoothing capacitor and the X capacitor to be discharged when the AC shutoff detection signal is output, and the discharging circuit includes a JFET which has a drain terminal connected to the above connection point and lowers discharge voltage; and a first discharging switch element connected to the source terminal of the JFET.

Abstract: A converter includes: a bridge diode; an X capacitor provided upstream of the bridge diode; a smoothing capacitor provided downstream of the bridge diode; an AC shutoff detection circuit which outputs an AC shutoff detection signal when input AC voltage is shut off; and a discharging circuit which is connected to a connection point at which the cathode of the bridge diode and the smoothing capacitor are connected, and allows residual charges in the smoothing capacitor and the X capacitor to be discharged when the AC shutoff detection signal is output, and the discharging circuit includes a JFET which has a drain terminal connected to the above connection point and lowers discharge voltage; and a first discharging switch element connected to the source terminal of the JFET.

Abstract: A switching power supply device including: a power transformer including a primary winding, a secondary winding, and an auxiliary winding; a switching element which is connected to the primary winding; an output voltage generation circuit which converts, into a direct-current voltage, a voltage induced in the secondary winding; a secondary-side on-time signal generation circuit which generates a secondary-side on-time signal indicating a secondary-side on-time; and a switching control circuit which controls a switching operation of the switching element so that the second direct-current voltage falls within a specified range, wherein the switching control circuit controls the switching operation so that the direct-current voltage becomes equal to or below an overvoltage specified value when the secondary-side on-time becomes smaller than a set value.

Abstract: A switching power supply device including: a power transformer including a primary winding, a secondary winding, and an auxiliary winding; a switching element which is connected to the primary winding; an output voltage generation circuit which converts, into a direct-current voltage, a voltage induced in the secondary winding; a secondary-side on-time signal generation circuit which generates a secondary-side on-time signal indicating a secondary-side on-time; and a switching control circuit which controls a switching operation of the switching element so that the second direct-current voltage falls within a specified range, wherein the switching control circuit controls the switching operation so that the direct-current voltage becomes equal to or below an overvoltage specified value when the secondary-side on-time becomes smaller than a set value.

Abstract: To provide a nonvolatile memory microcomputer with which a step of testing a microcomputer unit using a logic tester can be omitted, thereby reducing the testing cost. A memory tester supplies test data and expectation data to the nonvolatile memory microcomputer, and the nonvolatile memory microcomputer stores them in a nonvolatile memory. Subsequently, upon receiving an address signal, the nonvolatile memory outputs a test signal and an expectation signal based on test data and expectation data corresponding to the address signal. The test signal is supplied to a circuit block in the microcomputer unit, to drive the circuit block. The circuit block returns a test result signal, which is output to the memory tester together with the expectation signal. The memory tester compares the test result signal and the expectation signal, to judge whether the microcomputer unit operates correctly.

Abstract: To provide a nonvolatile memory microcomputer with which a step of testing a microcomputer unit using a logic tester can be omitted, thereby reducing the testing cost. A memory tester supplies test data and expectation data to the nonvolatile memory microcomputer, and the nonvolatile memory microcomputer stores them in a nonvolatile memory. Subsequently, upon receiving an address signal, the nonvolatile memory outputs a test signal and an expectation signal based on test data and expectation data corresponding to the address signal. The test signal is supplied to a circuit block in the microcomputer unit, to drive the circuit block. The circuit block returns a test result signal, which is output to the memory tester together with the expectation signal. The memory tester compares the test result signal and the expectation signal, to judge whether the microcomputer unit operates correctly.

Abstract: In halt period during standby time, a cell plate node potential switching circuit changes the potential of a cell plate node to a low potential that is lower than a high potential adopted in a burst refresh operation. As a result, a potential difference between both ends of a PN junction of a memory cell transistor is decreased, thereby suppressing a leakage current flowing through the PN junction. Simultaneously, a word driver circuit changes the potential of a word line to a negative potential that is lower than a normal potential adopted in the burst refresh operation. As a result, an off state of the memory cell transistor is enhanced owing to decrease of a gate-source voltage thereof, thereby suppressing a leakage current flowing from the bit line to a charge storage node.

Abstract: A digital input/output circuit to be connected between an internal data bus composed of 2.sup.n signal lines (n is zero or a positive integer) and 2.sup.n external terminals includes an output port for outputting data from the internal data bus to the external terminals and an input port for inputting the data from the external terminal to the internal data bus. The output port comprises a scrambler receiving data of 2.sup.n bits from the internal data bus and a mode signal and operating for relocating the received data in accordance with the mode signal so as to output the relocated data with each unit of 2.sup.m bits (m is an integer not greater than n) indicated by the mode signal. An output circuit includes 2.sup.n output buffers each having an input connected to receive directly or indirectly an output of the scrambler and an output connected to a corresponding one of the external terminals. This output circuit operates in response to the mode signal so as to make active 2.sup.m output buffers of the 2.