Patents by Inventor Tetsuyuki Rhee

Tetsuyuki Rhee has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5420821
    Abstract: A high-speed decoder for salvaging defective memory cells which has voltage generators VG0 and VG3 for generating voltages having binary logic levels corresponding to the bit information of each column of the addresses of defective memory cells. Upon input of a memory address signal, the voltage level of the bits of each column of the address signal are checked against the voltage levels corresponding to each column from the voltage generator. When all of the columns agree, an address agreement signal is generated by an address corroboration circuit including exclusive OR gates EX0 to EX3 and a NAND gate 10.
    Type: Grant
    Filed: October 6, 1993
    Date of Patent: May 30, 1995
    Assignee: Texas Instruments Incorporated
    Inventor: Tetsuyuki Rhee