Abstract: An information processing apparatus includes a plurality of cores that perform a plurality of respective tasks in parallel; and a plurality of cache memories that are provided corresponding to each of the plurality of cores and that store data to be referred to by the corresponding task at the time of execution, and wherein at least one of the plurality of cores is configured to: specify, for each of the cores, an overlap between the data referred to by the task that has been executed at the time of execution and data to be referred to by the task that is not yet executed at the time of execution, and executes the task that is not yet executed in a core having the largest overlap among the plurality of cores

Abstract: A parallel computer system includes a plurality of processing apparatuses that perform an arithmetic operation on elements of an array in parallel, wherein each of the plurality of processing apparatuses performs an arithmetic operation in a first axial direction on a first predetermined number of elements among elements disposed in the processing apparatus by different processing apparatuses, and stores the first predetermined number of elements having been subjected to the arithmetic operation in a storage device of the processing apparatus, and wherein at least some of the plurality of processing apparatuses acquire elements other than the first predetermined number of elements from each of the plurality of processing apparatuses, perform an arithmetic operation in the first axial direction on the acquired elements, and dispose a second predetermined number of elements having been subjected to the arithmetic operation in each of the plurality of processing apparatuses.

Abstract: A storage unit includes first to third storage areas. An operation unit executes, while executing a first process to perform an FFT (Fast Fourier Transform) operation by using the first storage area, a second process to transmit a calculated FFT calculation result stored in the second storage area to other processes and to store an FFT operation result received from said other processes in the third storage area.

Abstract: A storage unit includes first to third storage areas. An operation unit executes, while executing a first process to perform an FFT (Fast Fourier Transform) operation by using the first storage area, a second process to transmit a calculated FFT calculation result stored in the second storage area to other processes and to store an FFT operation result received from said other processes in the third storage area.

Abstract: A parallel computer system includes a plurality of processing apparatuses that perform an arithmetic operation on elements of an array in parallel, wherein each of the plurality of processing apparatuses performs an arithmetic operation in a first axial direction on a first predetermined number of elements among elements disposed in the processing apparatus by different processing apparatuses, and stores the first predetermined number of elements having been subjected to the arithmetic operation in a storage device of the processing apparatus, and wherein at least some of the plurality of processing apparatuses acquire elements other than the first predetermined number of elements from each of the plurality of processing apparatuses, perform an arithmetic operation in the first axial direction on the acquired elements, and dispose a second predetermined number of elements having been subjected to the arithmetic operation in each of the plurality of processing apparatuses.

Abstract: An information processing apparatus assigns the calculation of a first submatrix included in a matrix including zero elements and non-zero elements to a first thread and the calculation of a second submatrix included in the matrix to a second thread. The information processing apparatus compares the distribution of non-zero elements in the rows or columns of the first submatrix with the distribution of non-zero elements in the rows or columns of the second submatrix. The information processing apparatus determines allocation of storage areas for storing vectors to be respectively used in the calculations by the first and second threads, according to the result of the comparison.

Abstract: An information processing apparatus assigns the calculation of a first submatrix included in a matrix including zero elements and non-zero elements to a first thread and the calculation of a second submatrix included in the matrix to a second thread. The information processing apparatus compares the distribution of non-zero elements in the rows or columns of the first submatrix with the distribution of non-zero elements in the rows or columns of the second submatrix. The information processing apparatus determines allocation of storage areas for storing vectors to be respectively used in the calculations by the first and second threads, according to the result of the comparison.