Patents by Inventor Tetuo Biwa

Tetuo Biwa has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 4757362
    Abstract: A MOS transistor is featured by the provision of a conductive covering element for covering a drift channel region of the semiconductor device. The covering element is interposed by an insulating layer which is relatively thick. The covering element comprises a floating conductive element, disposed on the insulating layer, and a field plate means, disposed on a second insulating layer.
    Type: Grant
    Filed: May 27, 1981
    Date of Patent: July 12, 1988
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Tetuo Biwa, Kiyotoshi Nakagawa
  • Patent number: 4194214
    Abstract: High voltage diffusion-self-alignment metal oxide semiconductor devices and control logic circuitry therefor are integrated in a single semiconductor body. The integrated semiconductor device includes a considerably large number of output terminals compared to the number of input terminals. The output terminals develop signals of high voltages derived from the high voltage diffusion-self-alignment metal oxide semiconductor devices which are positioned at a peripheral zone of the semiconductor body.
    Type: Grant
    Filed: August 25, 1977
    Date of Patent: March 18, 1980
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katunobu Awane, Hironori Hattori, Tetuo Biwa, Hiroshi Tamaki
  • Patent number: 4058822
    Abstract: In a metal oxide semiconductor device of the diffusion-self-alignment type which comprises a semiconductor body having a conductivity of one type, a drain and a source regions having a conductivity opposite that of the semiconductor body, and a channel region of the same conductivity type as the semiconductor body and having a higher conductivity than that of the semiconductor body, said channel region being formed in such a manner to surround the source region through the use of double diffusion techniques. An active pinched resistor layer of the opposite conductivity type to that of the semiconductor body and having a lower conductivity than that of the drain and the source regions is formed on the surface of the semiconductor body to extend between the drain and the channel regions.
    Type: Grant
    Filed: June 1, 1976
    Date of Patent: November 15, 1977
    Assignee: Sharp Kabushiki Kaisha
    Inventors: Katunobu Awane, Hironori Hattori, Tetuo Biwa, Hiroshi Tamaki