Patents by Inventor Teturou Yamamoto

Teturou Yamamoto has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20120223930
    Abstract: An inverter circuit includes: a first transistor, a second transistor, a third transistor, a fourth transistor, and a fifth transistor; an input terminal and an output terminal; and a capacitor. The capacitor is inserted between a gate of the second transistor and one of a source and a drain of the second transistor in which the one is located on an output terminal side.
    Type: Application
    Filed: February 27, 2012
    Publication date: September 6, 2012
    Applicant: Sony Corporation
    Inventors: Teturou Yamamoto, Katsuhide Uchino
  • Patent number: 7355572
    Abstract: A pixel circuit, a display device, and a method of driving a pixel circuit able to obtain a source-follower output without luminance deterioration even when the current-voltage characteristic of a light emitting element changes due to aging, making a source-follower circuit of n-channel transistors possible, and in addition able to display uniform and high quality images not without regard to variations of threshold values and mobilities of the active elements inside pixels, wherein a capacitor C111 is connected between a gate and a source of a TFT 111, the source side of the TFT 111 is connected to a fixed potential (GND) through a TFT 114, a predetermined reference current Iref is supplied to the source of the TFT 111 with a predetermined timing, a voltage corresponding to the reference current Iref is held, and an input signal voltage centered about the voltage is coupled, whereby an EL light emitting element 19 is driven centered about the center value of variation of the mobilities.
    Type: Grant
    Filed: November 10, 2004
    Date of Patent: April 8, 2008
    Assignee: Sony Corporation
    Inventors: Katsuhide Uchino, Junichi Yamashita, Teturou Yamamoto
  • Patent number: 6903570
    Abstract: A bidirectional signal transmission circuit includes: a buffer element for reducing the impedance of a signal line; a signal line disposed between input terminals in both ends of the bidirectional signal transmission circuit; and a signal line disposed between output terminals in these ends. The signal lines are parallel to each other. A signal supplied from the exterior of the bidirectional signal transmission circuit is sequentially transmitted from one end to the other end of this circuit and is then output as an output signal from the other end in order to confirm the sequential transmission at the exterior. The transmitting direction is changeable between these ends in response to a switching signal supplied from the exterior. The buffer element for reducing the impedance of the signal line is disposed in at least one end of the signal line arranged between the output terminals.
    Type: Grant
    Filed: October 6, 2003
    Date of Patent: June 7, 2005
    Assignee: Sony Corporation
    Inventors: Kimitaka Kawase, Teturou Yamamoto, Katsuhide Uchino
  • Publication number: 20040100304
    Abstract: A bidirectional signal transmission circuit includes: a buffer element for reducing the impedance of a signal line; a signal line disposed between input terminals in both ends of the bidirectional signal transmission circuit; and a signal line disposed between output terminals in these ends. The signal lines are parallel to each other. A signal supplied from the exterior of the bidirectional signal transmission circuit is sequentially transmitted from one end to the other end of this circuit and is then output as an output signal from the other end in order to confirm the sequential transmission at the exterior. The transmitting direction is changeable between these ends in response to a switching signal supplied from the exterior. The buffer element for reducing the impedance of the signal line is disposed in at least one end of the signal line arranged between the output terminals.
    Type: Application
    Filed: October 6, 2003
    Publication date: May 27, 2004
    Inventors: Kimitaka Kawase, Teturou Yamamoto, Katsuhide Uchino