Abstract: An electronic device and a waterproof member of the electronic device are provided. The electronic device includes a device body, a cable, and a waterproof member. The device body includes a socket. The cable includes a plug unit and a cable body. The plug unit is disposed at one end of the cable body and is adapted to be connected to the socket. The waterproof member is sleeved over at least a portion of the plug unit and includes an elastic material.

Abstract: A rectilinear-block placement method includes disposing a first sub-block of each flexible block on a layout area of a chip canvas according to a reference position, generating an edge-depth map relative to first sub-blocks of flexible blocks on the layout area, predicting positions of second sub-blocks of the flexible blocks with depth values on the edge-depth map by a machine learning model, and positioning the second sub-blocks on the layout area according to the predicted positions of the second sub-blocks of the flexible blocks.

Abstract: A method forming a semiconductor package device includes: providing a substrate; forming a flip chip die on a first side on the substrate; and forming a molding compound on the first side of the substrate. The molding compound covers the flip chip die. The method further includes forming a heat sink on the molding compound; and forming a taping layer on a second side of the substrate, wherein the second side is opposite from the first side in a vertical direction. After forming the taping layer, the method further includes performing a pre-cut process and an etching process on the heat sink; and removing the taping layer.

Abstract: The application discloses a method and a system for shaping flexible blocks on a chip canvas in an integrated circuit design. An input is received describing geometric features of flexible blocks. A set of flexible blocks are generated based on the input. Obtained block areas of the set of flexible blocks are computed. Whether the set of flexible blocks are legal is determined based on determining whether area differences between the obtained block areas and a plurality of required areas for the set of flexible blocks meet a requirement. The set of flexible blocks are updated until the set of flexible blocks are all legal.

Abstract: A neural network based method places flexible blocks on a chip canvas in an integrated circuit (IC) design. The neural network receives an input describing geometric features of a flexible block to be placed on the chip canvas. The geometric features includes an area size and multiple aspect ratios. The neural network generates a probability distribution over locations on the chip canvas and the aspect ratios of the flexible block. Based on the probability distribution, a location on the chip canvas is selected for placing the flexible block with a chosen aspect ratio.

Abstract: An electronic device and a waterproof member of the electronic device are provided. The electronic device includes a device body, a cable, and a waterproof member. The device body includes a socket. The cable includes a plug unit and a cable body. The plug unit is disposed at one end of the cable body and is adapted to be connected to the socket. The waterproof member is sleeved over at least a portion of the plug unit and includes an elastic material.

Abstract: A method forming a semiconductor package device includes: providing a substrate; forming a flip chip die on a first side on the substrate; and forming a molding compound on the first side of the substrate. The molding compound covers the flip chip die. The method further includes forming a heat sink on the molding compound; and forming a taping layer on a second side of the substrate, wherein the second side is opposite from the first side in a vertical direction. After forming the taping layer, the method further includes performing a pre-cut process and an etching process on the heat sink; and removing the taping layer.

Abstract: A circuit test method for a test device to test a device under test is provided. The circuit test method includes the steps of applying zero volts to a plurality of power pins of the device under test; applying a test voltage to a first signal pin among a plurality of signal pins of the device under test; and measuring a current on a second signal pin among the plurality of signal pins of the device under test and determining whether there is a leakage current in the device under test.

Abstract: The invention introduces a method for wire bonding and testing, performed by wire-bonding equipment, including at least the following steps: providing a substrate and dies, where the substrate has exposed fingers and each die has exposed pads; controlling a motor to hold the substrate by a metal frame, where all the exposed fingers are floating from the metal frame to avoid ESD (electrostatic discharge) fail; and performing a wire bonding to make interconnections between the pads on the dies and the fingers on the substrate to fabricate a semi-finished flash-memory product.

Abstract: A circuit test method for a test device to test a device under test is provided. The circuit test method includes the steps of applying zero volts to a plurality of power pins of the device under test; applying a test voltage to a first signal pin among a plurality of signal pins of the device under test; and measuring a current on a second signal pin among the plurality of signal pins of the device under test and determining whether there is a leakage current in the device under test.

Abstract: The present invention provides a printed circuit board fabricated by a Non-Plating Process that includes at least one plating bar disposed around at least one package unit of the printed circuit board. The package unit includes at least one ground line, at least one power line and a plurality of signal lines. The ground line has a first contact pad exposed on a surface of the printed circuit board, and at least one of the ground lines is connected to the plating bar. The power line has a second contact pad exposed on the surface, and at least one of the power lines is connected to the neighboring plating bar. The signal line has a third contact pad exposed on the surface.

Abstract: The present invention provides a printed circuit board fabricated by a Non-Plating Process that includes at least one plating bar disposed around at least one package unit of the printed circuit board. The package unit includes at least one ground line, at least one power line and a plurality of signal lines. The ground line has a first contact pad exposed on a surface of the printed circuit board, and at least one of the ground lines is connected to the plating bar. The power line has a second contact pad exposed on the surface, and at least one of the power lines is connected to the neighboring plating bar. The signal line has a third contact pad exposed on the surface.

Abstract: The present invention provides a printed circuit board fabricated by a Non-Plating Process that includes at least one plating bar disposed around at least one package unit of the printed circuit board. The package unit includes at least one ground line, at least one power line and a plurality of signal lines. The ground line has a first contact pad exposed on a surface of the printed circuit board, and at least one of the ground lines is connected to the plating bar. The power line has a second contact pad exposed on the surface, and at least one of the power lines is connected to the neighboring plating bar. The signal line has a third contact pad exposed on the surface.

Abstract: The present invention provides a hydrophilic film that causes a liquid to diffuse rapidly in a single direction. The hydrophilic film comprises a substrate having a texture of parallel sunken and raised patterns, and a hydrophilic coat comprising a coat of silicon dioxide particles. The present invention also provides a method for preparing the hydrophilic film. The method comprises: preparing an aqueous dispersion of silicon dioxide particles, wherein the average size of the silicon dioxide particles is 1 to 60 nm, and the concentration of the silicon dioxide particles is 0.05% to 15% by weight; coating the aqueous dispersion of silicon dioxide particles on a substrate, wherein the substrate has a texture of parallel sunken and raised patterns; and drying the substrate coated with the aqueous dispersion of silicon dioxide particles.

Abstract: The present invention provides an ESD protection circuit including a discharge transistor, a first switch, a second switch, a third switch and a fourth switch. The discharge transistor forms a discharge path between a first voltage terminal and a second voltage terminal. The first switch selectively provides voltage at the first voltage terminal to a control terminal of the discharge transistor. The second switch selectively provides voltage at the second voltage terminal to the control terminal of the discharge transistor. The third switch selectively provides voltage at the first voltage terminal to a substrate of the discharge transistor. The fourth switch selectively provides voltage at second voltage terminal to the substrate of the discharge transistor.

Abstract: The present invention provides a hydrophilic film that causes a liquid to diffuse rapidly in a single direction. The hydrophilic film comprises a substrate having a texture of parallel sunken and raised patterns, and a hydrophilic coat comprising a coat of silicon dioxide particles. The present invention also provides a method for preparing the hydrophilic film. The method comprises: preparing an aqueous dispersion of silicon dioxide particles, wherein the average size of the silicon dioxide particles is 1 to 60 nm, and the concentration of the silicon dioxide particles is 0.05% to 15% by weight; coating the aqueous dispersion of silicon dioxide particles on a substrate, wherein the substrate has a texture of parallel sunken and raised patterns; and drying the substrate coated with the aqueous dispersion of silicon dioxide particles.

Abstract: The present invention provides an ESD protection circuit including a discharge transistor, a first switch, a second switch, a third switch and a fourth switch. The discharge transistor forms a discharge path between a first voltage terminal and a second voltage terminal. The first switch selectively provides voltage at the first voltage terminal to a control terminal of the discharge transistor. The second switch selectively provides voltage at the second voltage terminal to the control terminal of the discharge transistor. The third switch selectively provides voltage at the first voltage terminal to a substrate of the discharge transistor. The fourth switch selectively provides voltage at second voltage terminal to the substrate of the discharge transistor.

Abstract: A semiconductor device and an inductor are provided. The semiconductor device includes a top level interconnect metal layer (Mtop) pattern. A below-to-top level interconnect metal layer (Mtop?1) pattern is disposed directly below the top level interconnect metal layer pattern. A first via plug pattern is vertically disposed between the top level interconnect metal layer pattern and the below-to-top level interconnect metal layer pattern, electrically connected to the top level interconnect metal layer pattern and the below-to-top level interconnect metal layer pattern. The top level interconnect metal layer pattern, the below-to-top level interconnect metal layer pattern and the first via plug pattern have profiles parallel with each other from a top view.

Abstract: A display control device for a flat panel display is provided and includes a display controller and a timing controller. The display controller is provided for receiving an input signal and generating a display signal and a plurality of timing signals corresponding to the display signal. The timing controller includes a timing control unit and a data processing unit. The timing control unit is coupled to the display controller for providing a plurality of control signals required for the flat panel display. The data processing unit is incorporated into the display controller in a first integrated circuit chip for receiving the display signal and generating a plurality of output signals in synchronization with the timing signals. The output signals are output to the flat panel display through a predetermined interface.

Abstract: The invention provides an electrostatic discharge (ESD) protection device having an ESD path between a first circuit and a second circuit. The electrostatic discharge protection device includes a first doped region having a first conductive type. A first well has a second conductive type opposite to the first conductive type. A second doped region and a third doped region are in the first well, respectively having the first and second conductive types. The first doped region is coupled to a power supply terminal or a ground terminal of the first circuit, and the second and third doped regions are both coupled to a power supply terminal or a ground terminal of the second circuit, respectively.