Patents by Inventor Teymour M. Mansour

Teymour M. Mansour has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Configuration and testing of multiple-die integrated circuits
    Patent number: 9091727
    Abstract: In one embodiment, a configuration data sequence is input to a master programmable integrated circuit (IC). In response to control bits in the configuration data sequence, the master programmable IC transmits the configuration data sequence to one or more slave programmable ICs. The master programmable IC and the one or more slave programmable ICs are configured in parallel with configuration bits from the configuration data sequence.
    Type: Grant
    Filed: October 16, 2012
    Date of Patent: July 28, 2015
    Assignee: XILINX, INC.
    Inventors: Julian Lupu, Shivani C. Desai, Lee N. Chung, Teymour M. Mansour
  • Method and apparatus for testing programmable integrated circuits
    Patent number: 8082535
    Abstract: A method of testing an IC generates a test design list of test patterns and produces an arc usage string for each test pattern. The arc usage strings are ranked according to the number of untested arcs in each successive test pattern by comparing each of the remaining arc usage strings against an already-tested arc file to identify the arc usage string (test pattern) having the greatest number of untested arcs. A test sequence list of test patterns ranked in order of the most number of untested arcs to the least number of untested arcs is provided to a tester and the IC is tested in order of the test patterns on the test sequence list.
    Type: Grant
    Filed: February 3, 2009
    Date of Patent: December 20, 2011
    Assignee: Xilinx, Inc.
    Inventors: Ian L. McEwen, Teymour M. Mansour, Andrew G. Anderson, Reto Stamm
  • Method and apparatus for eliminating noise induced errors during test of a programmable logic device
    Patent number: 7558995
    Abstract: A method and apparatus for substantially eliminating noise induced errors caused by a premature start-up sequence between configuration of an integrated circuit (IC) and execution of functional test vectors. A noise elimination sequence is executed, whereby the configuration bitstream associated with the IC is scanned for the existence of a start-up sequence. If found, the start-up sequence is stripped from the configuration bitstream and the IC is then configured using the modified configuration bitstream. The input/output (I/O) pins of the IC remain in a deactivated state until a startup sequence is transmitted to the IC via a Joint Test Action Group (JTAG) port of the IC, which then allows IC testing to commence.
    Type: Grant
    Filed: November 21, 2005
    Date of Patent: July 7, 2009
    Assignee: Xilinx, Inc.
    Inventors: Randy J. Simmons, Teymour M. Mansour
  • Methods of resource optimization in programmable logic devices to reduce test time
    Patent number: 6944809
    Abstract: Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.
    Type: Grant
    Filed: August 6, 2002
    Date of Patent: September 13, 2005
    Assignee: Xilinx, Inc.
    Inventors: Andrew W. Lai, Randy J. Simmons, Teymour M. Mansour, Vincent L. Tong, Jeffrey V. Lindholm, Jay T. Young, William R. Troxel, Sridhar Krishnamurthy
  • Methods of resource optimization in programmable logic devices to reduce test time
    Publication number: 20040030975
    Abstract: Methods of optimizing the use of routing resources in programmable logic devices (PLDs) to minimize test time. A set of routing resources is identified that are not used in most designs, and a device model is provided to the user that prevents the use of these resources. Because the routing resources will never be used, they need not be tested by the PLD manufacturer, significantly reducing the test time. For example, each PLD within a PLD family is typically designed using a different number of similar tiles. Thus, smaller PLDs in the family include an unnecessarily large number of routing resources. These excessive routing resources can be disabled during implementation of a design. In another example, each tile along the edges of an array includes routing resources designed primarily to provide access to tiles that are not present. These redundant routing resources can be disabled during implementation of a design.
    Type: Application
    Filed: August 6, 2002
    Publication date: February 12, 2004
    Applicant: Xilinx, Inc.
    Inventors: Andrew W. Lai, Randy J. Simmons, Teymour M. Mansour, Vincent L. Tong, Jeffrey V. Lindholm, Jay T. Young, William R. Troxel, Sridhar Krishnamurthy