Patents by Inventor Tezaswi Raja

Tezaswi Raja has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20110211582
    Abstract: A method of sending signals, including data and timing information, between transportation units on a communication bus of an integrated circuit, by generating clock triggers for every transportation unit on the bus, thereby initiating each preceding one of the transportation units to start sending the signals in a wave-front to an adjacent succeeding one of the transportation units, where the wave-front is initiated at each of the transportation units at a common point in time, and every transportation unit applying a timing adjustment to at least one of the data and timing information that it receives in the signals from the preceding transportation unit, to at least one of (1) capture the data from the preceding transportation unit, (2) relay the data without modification from the preceding transportation unit to the succeeding transportation unit on the communication bus, and (3) load new data to the communication bus, with updated timing information in a succeeding wave-front.
    Type: Application
    Filed: November 19, 2008
    Publication date: September 1, 2011
    Applicant: LSI CORPORATION
    Inventors: Ting Zhou, Robin J. Tang, Ephrem C. Wu, Tezaswi Raja
  • Publication number: 20100333057
    Abstract: Various embodiments of systems and methods are disclosed for providing adaptive body bias control. One embodiment comprises a method for adaptive body bias control. One such method comprises: modeling parametric data associated with a chip design; modeling critical path data associated with the chip design; providing a chip according to the chip design; storing the parametric data and the critical path data in a memory on the chip; reading data from a parametric sensor on the chip; based on the data from the parametric sensor and the stored critical path and parametric data, determining an optimized bulk node voltage for reducing power consumption of the chip without causing a timing failure; and adjusting the bulk node voltage according to the optimized bulk node voltage.
    Type: Application
    Filed: June 29, 2009
    Publication date: December 30, 2010
    Inventors: Robin Tang, Ephrem Wu, Tezaswi Raja