Abstract: Demodulation and bit synchronization apparatus that uses a plurality of field programmable gate arrays to provide parallel processing to implement demodulation and bit synchronization. An analog-to-digital converter converts and demultiplexes applied intermediate frequency signals having a substantially wide bandwidth to output demultiplexed data signals at a lower clock rate. A digital signal processor processes the demultiplexed data signals to produce detected signals. A plurality of algorithms are implemented in the demodulator and bit synchronizer that include Costas loop demodulators, for example implemented using a carrier loop/lock detector, a direct digital synthesizer and a plurality of multipliers. Eight-tap T/2 baseband equalizers are implemented using in-phase and quadrature-phase accumulators and equalizers, and an in-phase/mid-phase bit synchronizer is implemented using the in-phase accumulator and a mid-phase accumulator and equalizer.

Abstract: The automatic gain control loop has an automatic gain control loop filter generating a multi-bit gain control word in response to the power level of the output signal of the loop. A shifter circuit shifts the input data by selected number of bits under the control of selected most significant bits of the gain control word multiplying the power of the input signal. A multiplier circuit multiplies the shifted data output from the shifter circuit by predetermined multiplication factors under the control of the remaining bits of the gain control word. The shifting and adding of the input data under the control of the gain control word maintains the power level of the output signal within a predetermined range.