Abstract: Disclosed are improved methods, systems, and computer program products for generating and optimizing an I/O ring arrangement for an electronic design. Corner packing is one approach that can be taken to optimizing an I/O ring. Stacking of I/O components provides another approach for optimizing an I/O ring.

Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays. An approach is described for performing memory mapping in the context of selecting an electronic product having an array of uncommitted logic.

Abstract: Disclosed are improved methods, systems, and computer program products for implementing an I/O ring structure to generate an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement. Nodes in the I/O ring structure are used to track objects in the I/O ring.

Abstract: Disclosed are improved methods, systems, and computer program products for generating an I/O ring arrangement for an electronic design, and for performing chip planning and estimation based upon the I/O ring arrangement.

Abstract: An improved approach is described for analyzing and estimating products having arrays of uncommitted logic, and matching these products to electronic designs. The approach can be applied to any type of product that include arrays of uncommitted logic, such as gate arrays and field programmable gate arrays.

Abstract: An improved method, system, and computer program product for selecting components for an early stage electronic design is disclosed. A library of cells is modeled and is characterized by parameter combinations, where the cell modeling information is based upon ranking and scoring of the cells in the cell library. Based upon design specification information for an electronic design, the cell modeling data is used to select one or more representative cells for the early stage design based upon the list of ranked cells. The rankings provide an indication of the appropriateness of the selected cells for the early stage design. The pre-modeling of the cells provides high efficiency at run-time when there is a need to quickly select cells for the early stage design.

Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.

Abstract: An improved method, system, and computer program product for selecting components for an early stage electronic design is disclosed. A library of cells is modeled and is characterized by parameter combinations, where the cell modeling information is based upon ranking and scoring of the cells in the cell library. Based upon design specification information for an electronic design, the cell modeling data is used to select one or more representative cells for the early stage design based upon the list of ranked cells. The rankings provide an indication of the appropriateness of the selected cells for the early stage design. The pre-modeling of the cells provides high efficiency at run-time when there is a need to quickly select cells for the early stage design.

Abstract: An improved method, system, user interface, and computer program product is described for performing power-related inferences for an electronic design. According to some approaches, the electronic design is configured to include multiple power domains. Design information is used to infer the existence of power-management structures for and between the power domains in the electronic design. A graphical user interface is provided to visualize the inferred power-related structures and to allow the user to interact with and modify the design information related to power management.

Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.

Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.

Abstract: Method and system for conducting design explorations of an integrated circuit are disclosed. In one embodiment, the method includes obtaining a design description of the integrated circuit that includes a virtual design block, creating a representative netlist for representing the virtual design block, where the representative netlist includes one or more soft design models, and each soft design model comprises one or more template cells for modeling a portion of the integrated circuit. The method further includes defining physical attributes for the one or more soft design models in accordance with area requirements of the virtual design block, where the one or more soft design models are described with flexible shape and pin locations, performing design explorations of the integrated circuit using the one or more soft design models and their corresponding template cells, and generating a representative implementation of the integrated circuit using results of the design explorations.