Abstract: Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.

Abstract: CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or ?processor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. Several frequency-adjusting techniques are presented which can be used in an distributed clock network environment which includes an array of oscillators. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of oscillators are described.

Abstract: A stealth mode technique records information onto the sound track of a camcorder without the knowledge of the user. Infrasound is continuously generated by an array of audio sources placed in a geographical position that potentially encompasses the location of the recording device. A database stores the known characteristics of all audio sources. Once the recorded media is released to the public, a post analysis using a processing unit can decompose the recording back into a set of reconstructed audio sounds. An analysis can be performed to determine which audio sounds match the reconstructed audio sounds so that an estimate of the set of parameters associated with the sound track can be obtained. The set of parameters includes the geographical location and local time of the recording. The geographic location provides the opportunity to capture the terrorists and free the hostages.

Abstract: Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.

Abstract: CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or ?processor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. Several frequency-adjusting techniques are presented which can be used in an distributed clock network environment which includes an array of oscillators. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of oscillators are described.

Abstract: Placing inductors or resistors in parallel causes the combined value of inductance or resistance to decrease according to the parallel combination rule. This invention decreases the parasitic resistance of an inductor by placing several inductors in parallel. Furthermore, by careful placement of these inductors, the mutual inductance between these inductors can be used to increase the equivalent inductance value to a value near that of the original inductance value of a single inductor. Thus, it is possible to create an inductance with a much lower value of parasitic resistance. This invention allows the formation of high Q inductors and would be beneficial in any circuit design requiring inductances. Another aspect of this invention is that the coils can be partitioned to minimize eddy current losses. This invention can easily be implemented in a planar technology. Simulations of several tank circuits indicate that the power dissipation can be reduced 3 to 4 times when compared to conventional techniques.

Abstract: CMOS LC tank circuits and flux linkage between inductors can be used to distribute and propagate clock signals over the surface of a VLSI chip or processor. The tank circuit offers an adiabatic behavior that recycles the energy between the reactive elements and minimizes losses in a conventional sense. Flux linkage can be used to orchestrate a number of seemingly individual and distributed CMOS LC tank circuits to behave as one unit. In one example, the distribution of a 45° separated multi-phase balanced oscillations over the surface of die 1.6 cm×1.6 cm at 10 GHz is expected to dissipate under 10 W and offers a potential to significantly reduce the road map predictions of 100 W. Simulations of several CMOS tank circuits indicate that the power dissipation can be reduced an order of magnitude when compared to conventional techniques. A passive flux linkage, mechanical, and finite state machine technique of frequency adjustment of an oscillator are described.

Abstract: Methods and apparatus are disclosed for adjusting the frequency tuning range of an oscillator circuit. The oscillator circuit is comprised of at least two MOS devices; a first reactance connecting a drain electrode of a first MOS device to a gate electrode of a second MOS device and a second reactance connecting a drain electrode of the second MOS device to a gate electrode of the first MOS device; and a tank circuit connected to the source and drain electrodes. The first and second reactance may comprises a capacitor or a diode or a combination thereof. In addition, one or more resistors may optionally be connected between a gate electrode of at least one of the MOS device and a power source.

Abstract: An integrated circuit comprises a plurality of integrated circuit die arranged in a stack, with a given die other than a top die of the stack carrying current for itself and at least one additional die of the stack via substrate conduction. In one arrangement, each of the die other than a bottom die of the stack carries its power supply current by substrate conduction via a bus or other power supply conductor of an underlying die.

Abstract: Electronic modules are interconnected with one another by means of communication (e.g., ultrasonic) links, In one embodiment, in a local conference call environment, only one wireless RF link is necessary—between a master cell phone and a base station, whereas all other voice modules are interconnected with one another and with the master via ultrasonic links. In another embodiment, a master voice module (with or without an RF link to a base station) includes at least one detachable module (e.g., an earpiece and/or mouthpiece) that is interconnected with the master via an ultrasonic link. In yet another embodiment, a detachable module includes a capacitor, which serves as its power supply and which is recharged when it is attached a master module (e.g., by a battery in the master module).

Abstract: Methods and apparatus are provided for preventing a third party from listening to a conversation between at least two participants on a telephone. The telephone generates an audio stimulus signal that is presented through a secondary speaker. The audio stimulus signal may be, for example, pseudorandom noise or a cancellation signal. According to one aspect of the invention, the telephone ensures that the audio stimulus signal does not significantly impair the conversation for the at least two participants. To prevent the third party from listening to the local portion of the conversation, the audio stimulus signal is subtracted from the received signal prior to presenting the received signal to the user. To prevent the third party from listening to the remote portion of the conversation, the audio stimulus signal is subtracted from the received signal.

Abstract: A variable capacitance circuit on an integrated circuit comprises a MOS transistor, and a capacitance multiplier connected to one end of a channel of the MOS device. A MOS device is formed in series with an inductance, and a capacitance multiplier is formed to be connected to a node between the MOS device and the inductance.

Abstract: A static latch circuit is used to suppress crosstalk glitch in a synchronous digital integrated circuit. A static latch is inserted into a selected victim net, and the net is examined if crosstalk glitch induced in the selected victim net is sufficiently suppressed. If not, then the selected victim net is examined to check whether the crosstalk glitch is primarily due to propagated noise from an earlier stage or due to noise injected in the selected victim net. If the crosstalk glitch is propagated from an earlier stage, then a second static latch is inserted before the state in which the first static latch is inserted. Alternatively, another static latch may be inserted in the selected victim net. Cell libraries including a variety of static latch circuit architectures can be designed.

Abstract: An integrated circuit die comprises an internal signal pad arranged at a location away from a periphery of the die, a peripheral signal pad arranged proximate the periphery of the die, and a switch coupled between the internal signal pad and the peripheral signal pad. The switch is configurable in at least a first state in which the internal signal pad is not operatively connected to the peripheral signal pad, and a second state in which the internal signal pad is operatively connected to the peripheral signal pad, responsive to a control signal having one of respective first and second signal characteristics. The switch is configured in the first state during normal operation of the integrated circuit die, and is configured in the second state to permit test access to the internal signal pad via the peripheral signal pad.

Abstract: Integrated circuit fabrication techniques are provided which allow non-horizontal/non-vertical wires to traverse the entire chip surface, rather than just the comers as in the conventional Manhattan geometry, while interconnecting circuit points. This is achieved by employing a variable rotational assignment methodology with respect to the interconnect layers or levels during the IC fabrication operation. These techniques thus eliminate the litho step problem, reduce interconnect distances and lessen the influence of capacitance interaction between interconnect wires.

Abstract: Techniques are disclosed for automatic generation of a location-indicative instruction displayable to one or more users in a communication system which includes a wireless network comprising a plurality of user devices adapted for communication with at least one access point device. A test of a communication link between at least one of the user devices and the access point device is initiated. Based at least in part on a result of the test, an instruction displayable to a user associated with a given one of the user devices is generated, the instruction being indicative of a location at which the given user device is expected to obtain a particular level of data throughput performance.