Patents by Inventor Thai Doan

Thai Doan has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10224396
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to deep trench isolation structures and methods of manufacture. The structure includes: at least one gate structure on a substrate; an interlevel dielectric material above the substrate; and a trench isolation structure extending into the substrate adjacent to the at least one gate structure and terminating in the interlevel dielectric material above the substrate.
    Type: Grant
    Filed: November 20, 2017
    Date of Patent: March 5, 2019
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Daisy Vaughn, Thai Doan
  • Patent number: 9922973
    Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches with deep trench depletion and isolation structures and methods of manufacture. The structure includes a bulk substrate with a fully depleted region below source and drain regions of at least one gate stack and confined by deep trench isolation structures lined with doped material.
    Type: Grant
    Filed: June 1, 2017
    Date of Patent: March 20, 2018
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Steven M. Shank, Anthony K. Stamper, John J. Ellis-Monaghan, Thai Doan
  • Publication number: 20170069518
    Abstract: An apparatus and method of etching. The apparatus including a support substrate having a top surface; a stack of a multiplicity of layers formed on the top surface of the support substrate from a lowermost layer on the top surface of the support substrate to a topmost layer that is furthest from the support substrate; and wherein an entirety of the top surface of the topmost layer is not planar and at least one of the multiplicity of layers that is not the topmost layer is an electrically conductive layer.
    Type: Application
    Filed: September 4, 2015
    Publication date: March 9, 2017
    Inventors: Brett Cucci, Thai Doan, Jeffrey P. Gambino, Rebecca K. Kelley, Jed H. Rankin, Daniel S. Vanslette
  • Patent number: 9406472
    Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.
    Type: Grant
    Filed: December 21, 2010
    Date of Patent: August 2, 2016
    Assignee: GLOBALFOUNDRIES INC.
    Inventors: Dinh Dang, Thai Doan, George A. Dunbar, III, Zhong-Xiang He, Russell T. Herrin, Christopher V. Jahnes, Jeffrey C. Maling, William J. Murphy, Anthony K. Stamper, John G. Twombly, Eric J. White
  • Patent number: 8846481
    Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.
    Type: Grant
    Filed: December 20, 2013
    Date of Patent: September 30, 2014
    Assignee: International Business Machines Corporation
    Inventors: Marc W. Cantell, Thai Doan, Jessica A. Levy, Qizhi Liu, William J. Murphy, Christa R. Willets
  • Patent number: 8722445
    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a plurality of discrete wires on a substrate. The method further includes forming a sacrificial cavity layer on the discrete wires. The method further includes forming trenches in an upper surface of the sacrificial cavity layer. The method further includes filling the trenches with dielectric material. The method further includes depositing metal on the sacrificial cavity layer and on the dielectric material to form a beam with at least one dielectric bumper extending from a bottom surface thereof.
    Type: Grant
    Filed: December 20, 2010
    Date of Patent: May 13, 2014
    Assignee: International Business Machines Corporation
    Inventors: Dinh Dang, Thai Doan, Jeffrey C. Maling, Anthony K. Stamper
  • Publication number: 20140113426
    Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.
    Type: Application
    Filed: December 20, 2013
    Publication date: April 24, 2014
    Applicant: International Business Machines Corporation
    Inventors: Marc W. Cantell, Thai Doan, Jessica A. Levy, Qizhi Liu, William J. Murphy, Christa R. Willets
  • Publication number: 20120313146
    Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.
    Type: Application
    Filed: June 8, 2011
    Publication date: December 13, 2012
    Applicant: International Business Machines Corporation
    Inventors: Marc W. Cantell, Thai Doan, Jessica A. Levy, Qizhi Liu, William J. Murphy, Christa R. Willets
  • Publication number: 20110315527
    Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.
    Type: Application
    Filed: December 21, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinh DANG, Thai DOAN, George A. DUNBAR, III, Zhong-Xiang HE, Russell T. HERRIN, Christopher V. JAHNES, Jeffrey C. MALING, William J. MURPHY, Anthony K. STAMPER, John G. TWOMBLY, Eric J. WHITE
  • Publication number: 20110316101
    Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a plurality of discrete wires on a substrate. The method further includes forming a sacrificial cavity layer on the discrete wires. The method further includes forming trenches in an upper surface of the sacrificial cavity layer. The method further includes filling the trenches with dielectric material. The method further includes depositing metal on the sacrificial cavity layer and on the dielectric material to form a beam with at least one dielectric bumper extending from a bottom surface thereof.
    Type: Application
    Filed: December 20, 2010
    Publication date: December 29, 2011
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinh DANG, Thai DOAN, Jeffrey C. MALING, Anthony K. STAMPER
  • Patent number: 7939896
    Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.
    Type: Grant
    Filed: November 6, 2009
    Date of Patent: May 10, 2011
    Assignee: International Business Machines Corporation
    Inventors: Dinh Dang, Thai Doan, Jessica Anne Levy, Max Gerald Levy, Alan Frederick Norris, James Albert Slinkman
  • Publication number: 20100084736
    Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.
    Type: Application
    Filed: November 6, 2009
    Publication date: April 8, 2010
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Dinh Dang, Thai Doan, Jessica Anne Levy, Max Gerald Levy, Alan Frederick Norris, James Albert Slinkman
  • Patent number: 7675121
    Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.
    Type: Grant
    Filed: October 8, 2007
    Date of Patent: March 9, 2010
    Assignee: International Business Machines Corporation
    Inventors: Dinh Dang, Thai Doan, Jessica Anne Levy, Max Gerald Levy, Alan Frederick Norris, James Albert Slinkman
  • Publication number: 20090090970
    Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.
    Type: Application
    Filed: October 8, 2007
    Publication date: April 9, 2009
    Inventors: Dinh Dang, Thai Doan, Jessica Anne Levy, Max Gerald Levy, Alan Frederick Norris, James Albert Slinkman
  • Publication number: 20090093092
    Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.
    Type: Application
    Filed: October 8, 2007
    Publication date: April 9, 2009
    Inventors: DINH DANG, Thai Doan, Jessica Anne Levy, Max Gerald Levy, Alan Frederick Norris, James Albert Slinkman
  • Patent number: 6559030
    Abstract: A method of forming a recessed polysilicon contact is provided. The method includes: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidizing the surface of the polysilicon in the trench using plasma oxidation; and removing an upper portion of the polysilicon from the trench.
    Type: Grant
    Filed: December 13, 2001
    Date of Patent: May 6, 2003
    Assignee: International Business Machines Corporation
    Inventors: Thai Doan, Zhong-Xiang He, Michael P. McMahon