Abstract: A system for intelligent editing of legal documents. The system includes a computing device. The computing device is configured to access a plurality of legal source texts from a plurality of legal sources, generate a score for each of the plurality of legal source texts, train a natural language processing model as a function of the scored legal source texts and a first machine-learning process, receive user inputted legal text from a user device being operated by a human user to create a user legal document, analyze the user inputted legal text using the natural language processing model, suggest, as a function of the analyzing, a modification to a target text of the user inputted legal text, and generate a score for a modified user legal document. A method for intelligent editing of legal documents is also provided.

Abstract: A system for intelligent editing of legal documents. The system includes a computing device. The computing device is configured to access a plurality of legal source texts from a plurality of legal sources, generate a score for each of the plurality of legal source texts, train a natural language processing model as a function of the scored legal source texts and a first machine-learning process, receive user inputted legal text from a user device being operated by a human user to create a user legal document, analyze the user inputted legal text using the natural language processing model, suggest, as a function of the analyzing, a modification to a target text of the user inputted legal text, and generate a score for a modified user legal document. A method for intelligent editing of legal documents is also provided.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to deep trench isolation structures and methods of manufacture. The structure includes: at least one gate structure on a substrate; an interlevel dielectric material above the substrate; and a trench isolation structure extending into the substrate adjacent to the at least one gate structure and terminating in the interlevel dielectric material above the substrate.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to switches with deep trench depletion and isolation structures and methods of manufacture. The structure includes a bulk substrate with a fully depleted region below source and drain regions of at least one gate stack and confined by deep trench isolation structures lined with doped material.

Abstract: An apparatus and method of etching. The apparatus including a support substrate having a top surface; a stack of a multiplicity of layers formed on the top surface of the support substrate from a lowermost layer on the top surface of the support substrate to a topmost layer that is furthest from the support substrate; and wherein an entirety of the top surface of the topmost layer is not planar and at least one of the multiplicity of layers that is not the topmost layer is an electrically conductive layer.

Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.

Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a plurality of discrete wires on a substrate. The method further includes forming a sacrificial cavity layer on the discrete wires. The method further includes forming trenches in an upper surface of the sacrificial cavity layer. The method further includes filling the trenches with dielectric material. The method further includes depositing metal on the sacrificial cavity layer and on the dielectric material to form a beam with at least one dielectric bumper extending from a bottom surface thereof.

Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.

Abstract: Disclosed is a transistor structure, having a completely silicided extrinsic base for reduced base resistance Rb. Specifically, a metal silicide layer covers the extrinsic base, including the portion of the extrinsic base that extends below the upper portion of a T-shaped emitter. One exemplary technique for ensuring that the metal silicide layer covers this portion of the extrinsic base requires tapering the upper portion of the emitter. Such tapering allows a sacrificial layer below the upper portion of the emitter to be completely removed during processing, thereby exposing the extrinsic base below and allowing the metal layer required for silicidation to be deposited thereon. This metal layer can be deposited, for example, using a high pressure sputtering technique to ensure that all exposed surfaces of the extrinsic base, even those below the upper portion of the emitter, are covered.

Abstract: Planar cavity Micro-Electro-Mechanical System (MEMS) structures, methods of manufacture and design structure are provided. The method includes forming at least one Micro-Electro-Mechanical System (MEMS) cavity having a planar surface using a reverse damascene process.

Abstract: A method of forming at least one Micro-Electro-Mechanical System (MEMS) includes forming a plurality of discrete wires on a substrate. The method further includes forming a sacrificial cavity layer on the discrete wires. The method further includes forming trenches in an upper surface of the sacrificial cavity layer. The method further includes filling the trenches with dielectric material. The method further includes depositing metal on the sacrificial cavity layer and on the dielectric material to form a beam with at least one dielectric bumper extending from a bottom surface thereof.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Abstract: A low resistance contact structure and method of making the structure. The structure includes a polysilicon contact through an upper silicon layer and buried oxide layer to a lower silicon layer of a silicon-on-insulation substrate. A region of the upper silicon layer surrounds the polysilicon contact and top surface of the polysilicon contact and surrounding region of upper silicon layer are metal silicided providing an extended contact area greater than the area of the top surface of polysilicon contact.

Abstract: A method of forming a recessed polysilicon contact is provided. The method includes: forming a trench in a substrate; overfilling the trench with polysilicon; removing the polysilicon outside of the trench to provide a substantially planar surface; oxidizing the surface of the polysilicon in the trench using plasma oxidation; and removing an upper portion of the polysilicon from the trench.