Abstract: A current sourcing and sinking circuit for driving a charge pump for a voltage-controlled oscillator includes two similar subcircuits, each of which is capable of simultaneously sourcing and sinking output currents. Both subcircuits have identical, corresponding CMOSFET components with two open drain outputs, one of which is a current sourcing output port and the other of which is a current sinking output port. In one subcircuit the current sourcing output port is used while the current sinking output port is terminated drain-to-source with a short circuit. In the other subcircuit the current sinking output port is used while the current sourcing output port is terminated drain-to-source with a short circuit. The similarity of the two subcircuits provides a balanced current sourcing and sinking circuit topology, resulting in substantially equal source and sink current amplitudes and current sourcing and sinking activation timing.

Abstract: A low noise logic amplifier with an input signal converter and a differential logic amplifier which together receive and convert a nondifferential input logic signal to a differential output logic signal. The input signal converter receives the nondifferential logic signal and converts it to a differential input logic signal for the differential logic amplifier. The differential logic amplifier has two output signal current paths for its bias current. The input signal converter provides the differential input logic signal with a delay between its two differential logic phases such that at least one of the two output signal current paths in the differential logic amplifier is continuously conducting the bias current.

Abstract: An electrical circuit is disclosed which implements a CMOS to ECL translator with an incorporated latch. The invention provides a circuit which uses a small number of devices, and provides fast transition times with low power consumption.

Abstract: A low static power, digital signal level translator for translating an unbalanced digital signal to a balanced digital signal with a greater dynamic signal range includes two complementary MOSFET latches and a complementary MOSFET output buffer amplifier. The two latches each receive an unbalanced digital input signal (e.g. with TTL voltage levels) and translate it to a second unbalanced digital signal and an asymmetrically balanced digital signal. The symmetrically biased, output buffer amplifier receives these signals and produces therefrom a symmetrically balanced digital output signal with a greater dynamic signal range (e.g. with .+-.10 volt levels).

Abstract: A CMOS switch driver capable of driving a plurality of CMOS switches is disclosed. A pair of cascade coupled output inverters provide the complementary driver outputs. Their inputs are obtained respectively from the first of the pair and a third, or input, inverter. The circuit includes resistance elements in the output inverters that greatly reduce current spikes.