Abstract: An adjustable toilet seat handle including a clamping assembly, a spring member, and a knob is provided. The clamping assembly having a first clamp and a second clamp is removably connected to an undersurface of a toilet seat. A spring member connects the first clamp to the second clamp for defining a receptacle that compression fits the undersurface of the toilet seat. The spring member is operably connected to a lower surface of the clamping assembly and extends a distance between the first clamp and the second clamp to allow the undersurface of the toilet seat to be compression fitted in the receptacle. The knob is rigidly attached to and extends outwardly from the first clamp and can be gripped by a user to allow the user to raise or lower the toilet seat without direct contact with the toilet seat.

Abstract: An adjustable toilet seat handle including a clamping assembly, a spring member, and a knob is provided. The clamping assembly having a first clamp and a second clamp is removably connected to an undersurface of a toilet seat. A spring member connects the first clamp to the second clamp for defining a receptacle that compression fits the undersurface of the toilet seat. The spring member is operably connected to a lower surface of the clamping assembly and extends a distance between the first clamp and the second clamp to allow the undersurface of the toilet seat to be compression fitted in the receptacle. The knob is rigidly attached to and extends outwardly from the first clamp and can be gripped by a user to allow the user to raise or lower the toilet seat without direct contact with the toilet seat.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Abstract: The present invention allows for the simultaneous transmission of two digital signals from one integrated circuit to another. The two digital signals are encoded utilizing a voltage divider circuit and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded digital signal to further decode the second digital signal.

Abstract: A driver circuit including of one or more fingers, or parallel driver circuits, senses for an overshoot or an undershoot condition of the signal transmitted onto a transmission line coupled to the driver circuit and compensates for such an overshoot or an undershoot by temporarily turning off the offending transition portion of the driver circuit, or finger portion. This is accomplished by turning off the transistor applying one of the two supply voltages coupled to the output transmission line. Effectively, the compensation circuitry within the driver circuit more closely matches the output impedance of the driver circuit to the impedance on the driven transmission line.

Abstract: The present invention allows for the simultaneous transmission of three digital signals from one integrated circuit to another. The three digital signals are encoded utilizing series resistors of predetermined values and are then transmitted by one transmission line to the second integrated circuit chip. The second integrated circuit chip decodes the first digital signal and then utilizes this decoded first digital signal to further decode the second digital signal, and then utilizes the decoded first and second digital signals to decode the third digital signal.

Abstract: The present invention facilitates communication of signals from circuitry implemented with a first CMOS technology requiring a first voltage level supply for operation to circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation, wherein the first and second voltage level supplies are not equal. The present invention receives from the circuitry implemented with a first CMOS technology a signal which has a first voltage level that is not acceptable for input into the circuitry implemented with a second CMOS technology. This signal is converted to a second voltage level that is acceptable for input into the circuitry implemented with a second CMOS technology, and then transmitted to the circuitry implemented with a second CMOS technology requiring a second voltage level supply for operation.