Patents by Inventor Thanapandi G

Thanapandi G has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • High to low level shifter architecture using lower voltage devices
    Patent number: 11923852
    Abstract: A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (I/O) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.
    Type: Grant
    Filed: September 28, 2021
    Date of Patent: March 5, 2024
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Prateek Mishra, Thanapandi G, Jagadeesh Anathahalli Singrigowda, Dhruvin Devangbhai Shah, Girish Anathahalli Singrigowda, Animesh Jain
  • HIGH TO LOW LEVEL SHIFTER ARCHITECTURE USING LOWER VOLTAGE DEVICES
    Publication number: 20230098336
    Abstract: A voltage level-shifting circuit for an integrated circuit includes an input terminal receiving a voltage signal referenced to an input/output (PO) voltage level. A transistor overvoltage protection circuit includes a first p-type metal oxide semiconductor (PMOS) transistor includes a source coupled to the second voltage supply, a gate receiving an enable signal, and a drain connected to a central node. A first n-type metal oxide semiconductor (NMOS) transistor includes a drain connected to the central node, a gate connected to the input terminal, and a source connected to an output terminal. A second NMOS transistor includes a drain connected to the input terminal, a gate connected to the central node, and a source connected to the output terminal.
    Type: Application
    Filed: September 28, 2021
    Publication date: March 30, 2023
    Applicant: Advanced Micro Devices, Inc.
    Inventors: Prateek Mishra, Thanapandi G, Jagadeesh Anathahalli Singrigowda, Dhruvin Devangbhai Shah, Girish Anathahalli Singrigowda, Animesh Jain