Abstract: An ejector latch indicator light and connector assembly for reducing the interference by a bulkhead of light emitted from an indicator light and establishing an electrical connection between an ejector latch and a printed circuit board (PCB) is disclosed. In one embodiment, the present invention is comprised of an ejector latch. The present embodiment is further comprised of an indicator light integrated with the ejector latch. The indicator light adapted to emit light from the ejector latch such that interference by the bulkhead of the light emitted from the indicator light is reduced. The present embodiment is also comprised of a compression-fit connector integrated with the ejector latch. The compression-fit connector adapted to provide a removably coupleable electrical connection between the ejector latch and a printed circuit board (PCB) such that inadvertent disconnection of the removably coupleable electrical connection between the ejector latch and the PCB is reduced.

Abstract: An ejector latch connector assembly for establishing an electrical connection between an ejector latch and a printed circuit board (PCB) is disclosed. In one embodiment, the present invention is comprised of an ejector latch. The present embodiment is further comprised of a compression-fit connector integrated with the ejector latch. The compression-fit connector adapted to provide a removably coupleable electrical connection between the ejector latch and a printed circuit board (PCB) such that inadvertent disconnection of the removably coupleable electrical connection between the ejector latch and the PCB is reduced.

Abstract: An ejector latch indicator light assembly for reducing the interference by a bulkhead of light emitted from an indicator light is disclosed. In one embodiment, the present invention is comprised of an ejector latch. The present embodiment is further comprised of an indicator light integrated with the ejector latch. The indicator light adapted to emit light from the ejector latch such that interference by the bulkhead of the light emitted from the indicator light is reduced.

Abstract: A method and apparatus to mount a capacitor plate to a substrate, under a component. One embodiment of the invention involves a method to assemble a capacitor plate on a substrate. A second embodiment of the invention involves a method to fabricate a capacitor plate. A third embodiment of the invention involves an assembled substrate with a capacitor plate on the second side of the assembled substrate, under an electrical contact area of a component on the first side of the assembled substrate.

Abstract: A cPCI server system includes a plurality of printed circuit assemblies. A server management card coupled to the plurality of printed circuit assemblies monitors and manages operation of the server system. The server management card receives and stores status information from the plurality of printed circuit assemblies. A first LCD panel is mounted on the server system and is coupled to the server management card. The first LCD panel provides a user interface for configuring the server management card and accessing the stored status information from the server management card.

Abstract: The present invention, in various embodiments, provides techniques for reducing effects of electrical impedance. In one embodiment, the impedance is in the form of inductance and arises from vias in a termination PCB and from resistors used on the PCB. In one embodiment, a power plane is placed near the resistors. Additional power and ground planes are created in parallel among themselves and perpendicular to the vias, which cause capacitance to be formed between each pair of the ground and power planes, the ground planes and the vias, and the power planes and the vias. In one aspect, the power plane near the resistors and the formed capacitance allow the high-frequency returned currents to flow through a smaller loop and thus be affected by a smaller inductance. Additionally, the created capacitance reduces both the total impedance of the vias and the resistors and any impedance that result from power-ground discontinuity.

Abstract: A system and method intelligently control power consumption of distributed services using a computer system that provides independent computing elements each capable of entering a power saving mode. In accordance with the present invention, three different algorithms are disclosed. The first algorithm is a reduced load power saving algorithm. As the load decreases, duplicate instances of services can be gracefully suspended and the host processor cards hosting these instances can enter a power saving mode. The second algorithm is a priority-based power consumption reduction algorithm. If power consumption must be reduced, services having less of a contribution to revenue are suspended before components that having a higher contribution to revenue. The third algorithm is a minimal power-consuming redundant computing hardware algorithm that allows a “cold spare” host processing card to be pressed into service if another card fails.

Abstract: A system and method intelligently control power consumption of distributed services using a computer system that provides independent computing elements each capable of entering a power saving mode. In accordance with the present invention, three different algorithms are disclosed. The first algorithm is a reduced load power saving algorithm. As the load decreases, duplicate instances of services can be gracefully suspended and the host processor cards hosting these instances can enter a power saving mode. The second algorithm is a priority-based power consumption reduction algorithm. If power consumption must be reduced, services having less of a contribution to revenue are suspended before components that having a higher contribution to revenue. The third algorithm is a minimal power-consuming redundant computing hardware algorithm that allows a “cold spare” host processing card to be pressed into service if another card fails.

Abstract: A system and method intelligently control power consumption of distributed services using a computer system that provides independent computing elements each capable of entering a power saving mode. In accordance with the present invention, three different algorithms are disclosed. The first algorithm is a reduced load power saving algorithm. As the load decreases, duplicate instances of services can be gracefully suspended and the host processor cards hosting these instances can enter a power saving mode. The second algorithm is a priority-based power consumption reduction algorithm. If power consumption must be reduced, services having less of a contribution to revenue are suspended before components that having a higher contribution to revenue. The third algorithm is a minimal power-consuming redundant computing hardware algorithm that allows a “cold spare” host processor card to be pressed into service if another card fails.

Abstract: A method and apparatus controls fans and power supplies to provide accelerated run-in testing. By modulating fans to increase case temperatures and adjusting power supplies to provide “worst case” voltages, a computer system can be subjected to a run-in tests under taxing conditions. By alternately cooling and heating devices such as CPUs, devices can be subjected to mechanical stresses associated with power-on/power off cycles. A time based test implements the present invention based on time, and a temperature based test implements the present invention based on temperature. The present invention can be used to implement a run-in test in which the computer system is operated at an elevated temperature, thereby achieving results similar to those achieved by performing a run-in test in an environmental chamber at an elevated temperature. Alternatively, the a run-in test can be performed by repeatedly cycling the temperature between relatively high and low values.

Abstract: A server system includes a plurality of printed circuit assemblies including at least one host processor card. A management card is coupled to the plurality of printed circuit assemblies. The management card is dedicated to monitoring and managing operation of the server system, including monitoring and managing on-line insertion and removal of the printed circuit assemblies in a compact peripheral component interconnect (cPCI) server system.

Abstract: A cPCI server system includes a plurality of host processor cards. A management card is coupled to the plurality of host processor cards via at least one bus. The management card includes at least one user interface for receiving network address information from a user. The management card is configured to send received network address information to the plurality of host processor cards via the at least one bus, thereby configuring the host processor cards for management LAN communications.

Abstract: A cPCI server system includes a plurality of printed circuit assemblies, including at least one host processor card. A server management card is coupled to the plurality of printed circuit assemblies for monitoring and managing operation of the server system. The server management card receives and stores status information from the plurality of printed circuit assemblies. The server management card includes a plurality of interfaces for configuring the server management card and accessing the stored status information from the server management card.

Abstract: A cPCI server system includes a plurality of printed circuit assemblies. A server management card coupled to the plurality of printed circuit assemblies monitors and manages operation of the server system. The server management card receives and stores status information from the plurality of printed circuit assemblies. A first LCD panel is mounted on the server system and is coupled to the server management card. The first LCD panel provides a user interface for configuring the server management card and accessing the stored status information from the server management card.

Abstract: A cPCI server system includes a plurality of subsystems, each including an associated memory for storing power usage information. A power supply unit coupled to the plurality of subsystems provides power to the plurality of subsystems. A server management card is coupled to the plurality of subsystems. The server management card is configured to retrieve the power usage information from the memory of each subsystem. The server management card is configured to calculate the total power usage of the plurality of subsystems based on the retrieved power usage information.

Abstract: A cPCI server system includes a plurality of host processor cards for providing management LAN communications and payload LAN communications. A first card is coupled to the plurality of host processor cards and is coupled to a payload LAN. The plurality of host processor cards are configured to provide payload LAN communications through the first card. A second card is coupled to the plurality of host processor cards and can be optionally coupled to a management LAN. The plurality of host processor cards are configured to provide management LAN communications with the management LAN through the second card.

Abstract: The present invention, in various embodiments, provides techniques for reducing effects of electrical impedance. In one embodiment, the impedance is in the form of inductance and arises from vias in a termination PCB and from resistors used on the PCB. In one embodiment, a power plane is placed near the resistors. Additional power and ground planes are created in parallel among themselves and perpendicular to the vias, which cause capacitance to be formed between each pair of the ground and power planes, the ground planes and the vias, and the power planes and the vias. In one aspect, the power plane near the resistors and the formed capacitance allow the high-frequency returned currents to flow through a smaller loop and thus be affected by a smaller inductance. Additionally, the created capacitance reduces both the total impedance of the vias and the resistors and any impedance that result from power-ground discontinuity.

Abstract: A method and apparatus to mount a capacitor plate to a substrate, under a component. One embodiment of the invention involves a method to assemble a capacitor plate on a substrate. A second embodiment of the invention involves a method to fabricate a capacitor plate. A third embodiment of the invention involves an assembled substrate with a capacitor plate on the second side of the assembled substrate, under an electrical contact area of a component on the first side of the assembled substrate.

Abstract: A method and apparatus to mount a data capture plate to a substrate, under a component. One embodiment of the invention involves a method to assemble a data capture plate on a substrate. A second embodiment of the invention involves a method to fabricate a data capture plate. A third embodiment of the invention involves an assembled substrate including a data capture plate on the second side of the assembled substrate, under an electrical contact area of a component on the first side of the assembled substrate.

Abstract: A CompactPCI-based computer system including a chassis and a mid-plane board. The mid-plane board forms bus circuitry, and is positioned between a front and back of the chassis. The chassis and the mid-plane board combine to define a plurality of CompactPCI form factor slots, including front slots and back slots. At least one of the front slots and at least one of the back slots are system slots configured to receive and provide independent bus connections for respective CompactPCI form factor system processor cards. In one preferred embodiment, the mid-plane board is configured to provide a bussed connector at a first front slot and at a second back slot, and a transition connection at a first back slot and a second front slot. With this one preferred embodiment, a one- or two-unit wide system processor card can be loaded into the first front slot, and another one- or two-unit wide system processor card can be loaded into the second back slot.