Abstract: A superscalar microprocesor is provided that includes a predecode unit adapted for predecoding variable byte-length instructions. The predecode unit predecodes the instructions prior to their storage within an instruction cache. In one system, a predecode unit is configured to generate a plurality of predecode bits for each instruction byte. The plurality of predecode bits associated with each instruction byte are collectively referred to as a predecode tag. An instruction alignment unit then uses the predecode tags to dispatch the variable byte-length instructions simultaneously to a plurality of decode units which form fixed issue positions within the superscalar microprocessor. By utilizing the predecode information from the predecode unit, the instruction alignment unit may be implemented with a relatively small number of cascaded levels of logic gates, thus accommodating very high frequencies of operation.

Abstract: An apparatus is provided, including one or more early address generation units which attempt to perform data address generation upon decode of an instruction which includes a memory operand. The early address generation units may be successful at generating the data address if the logical data address is formed from a displacement only. Additionally, the early address generation unit may be successful at generating the data address if the logical data address is formed from the displacement and register operands which are available upon decode of the instruction. Data address generation latency may be shortened. If register operands are employed for forming the address and the register operands are not available, the data address may be generated in a functional unit at the execute stage.

Abstract: A shared branch prediction mechanism is provided in which a pool of branch prediction storage locations are shared among the multiple cache lines comprising a row of the instruction cache. The branch prediction storage locations within the pool are dynamically redistributed among the cache lines according to the number of branch instructions within each cache line. A cache line having a large number of branch instructions may be allocated more branch prediction storage locations than a cache line having fewer branch instructions. A prediction selector is included for each cache line in the instruction cache. The prediction selector indicates the selection of one or more branch prediction storage locations which store branch predictions corresponding to the cache line. In one embodiment, the prediction selector comprises multiple branch selectors.

Abstract: A microprocessor employing an apparatus for performing special register writes without serialization is provided. The apparatus detects special register write instructions when the instructions are dispatched, and stores an indication of the write in a special register dependency block. Instructions subsequent to the special register write instruction are examined for both explicit and implicit dependencies upon the special register write. If a dependency is detected with respect to a particular instruction, the instruction is dispatched to a reservation station along with an indication of the dependency. Instructions subsequent to the special register write instruction which are not dependent upon the special register are dispatched without an indication of special register dependency. Instructions without dependencies may speculatively execute prior to instructions with dependencies, or even prior to the special register write instruction.

Abstract: A reorder buffer is provided which stores a last in buffer (LIB) indication corresponding to each instruction. The last in buffer indication indicates whether or not the corresponding instruction is last, in program order, of the instructions within the buffer to update the storage location defined as the destination of that instruction. The LIB indication is included in the dependency checking comparisons. A dependency is indicated for a given source operand and a destination operand within the reorder buffer if the operand specifiers match and the corresponding LIB indication indicates that the instruction corresponding to the destination operand is last to update the corresponding storage location. At most one of the dependency comparisons for a given source operand can indicate dependency. According to one embodiment, the reorder buffer employs a line-oriented configuration.

Abstract: A microprocessor employing a DSP unit and an instruction decode unit is provided. The instruction decode unit is configured to detect an instruction field included with an instruction, and to dispatch instructions having the instruction field to the DSP unit. The DSP unit performs DSP functions, such as a multiply-accumulate function. In one embodiment, the inclusion of an instruction prefix field in an .times.86 instruction indicates that the instruction is a DSP instruction. In one particular implementation, the inclusion of a segment override prefix byte within the prefix field of an .times.86 instruction indicates that the instruction is a DSP instruction. Embodiments of the DSP unit may include a vector memory for storing operands. A block of operands may be stored into the vector memory prior to initiating a large number of DSP operations upon the block of operands.

Abstract: A dependency checking structure is provided which compares memory accesses performed from the execution stage of the instruction processing pipeline to memory accesses performed from the decode stage. The decode stage performs memory accesses to a stack cache, while the execution stage performs its accesses (address for which are formed via indirect addressing) to the stack cache and to a data cache. If a read memory access performed by the execution stage is dependent upon a write memory access performed by the decode stage, the read memory access is stalled until the write memory access completes. If a read memory access performed by the decode stage is dependent upon a write memory access performed by the execution stage, then the instruction associated with the read memory access and subsequent instructions are flushed. Data coherency is maintained between the pair of caches while allowing stack-relative accesses to be performed from the decode stage.

Abstract: A superscalar microprocessor is provided employing a way prediction unit which predicts the next fetch address as well as the way of the instruction cache that the current fetch address hits in while the instructions associated with the current fetch are being read from the instruction cache. The microprocessor may achieve high frequency operation while using an associative instruction cache. An instruction fetch can be made every clock cycle using the predicted fetch address from the way prediction unit until an incorrect next fetch address or an incorrect way is predicted. The instructions from the predicted way are provided to the instruction processing pipelines of the superscalar microprocessor each clock cycle.

Abstract: A data memory unit having a load/store unit and a data cache is provided which allows store instructions that are part of a load-op-store instruction to be executed with one access to a data cache. The load/store unit is configured with a load/store buffer having a checked bit and a way field for each buffer storage location. For load-op-store instructions, the checked bit associated with the store portion of the of the instruction is set when the load portion of the instruction accesses and hits the data cache. Also, the way field associated with the store portion is set to the way of the data cache in which the load portion hits. The data cache is configured with a locking mechanism for each cache line stored in the data cache. When the load portion of a load-op-store instruction is executed, the associated line is locked such that the line will remain in the data cache until a store instruction executes. In this way, the store portion of the load-op-store instruction is guaranteed to hit the data cache.

Abstract: An apparatus including a banked instruction cache and a branch prediction unit is provided. The banked instruction cache allows multiple instruction fetch addresses (comprising consecutive instruction blocks from the predicted instruction stream being executed by the microprocessor) to be fetched concurrently. The instruction cache provides an instruction block corresponding to one of the multiple fetch addresses to the instruction processing pipeline of the microprocessor during each consecutive clock cycle, while additional instruction fetch addresses from the predicted instruction stream are fetched. Preferably, the instruction cache includes at least a number of banks equal to the number of clock cycles consumed by an instruction cache access. In this manner, instructions may be provided during each consecutive clock cycle even though instruction cache access time is greater than the clock cycle time of the microprocessor.

Abstract: An apparatus for aligning variable byte length instructions to a plurality of issue positions is provided. The apparatus includes a byte queue divided into several subqueues. Each subqueue is maintained such that a first instruction in program order within the subqueue is identified by information stored in a first position within the subqueue, a second instruction in program order within the subqueue is identified by information stored in a second position within the subqueue, etc. When instructions from a subqueue are dispatched, remaining instructions within the subqueue are shifted such that the first of the remaining instructions (in program order) occupies the first position, etc. Instructions are shifted from subqueue to subqueue when each of the instructions within a particular subqueue have been dispatched. The information stored in one subqueue is shifted as a unit to another subqueue independent of the internal shifting of subqueue information.

Abstract: A register file including multiple register storages and multiple read ports is provided. Each register storage stores a subset of the architected register set for the microprocessor within which the register file is employed. Each register storage is coupled to select ones of the multiple read ports, reducing wiring and complexity of the register file. Each read port is coupled to a subset of the registers within the register file. The subset of the registers to which the read port is coupled is defined by the register storage(s) to which the read port is coupled. Access to a particular register is thereby restricted to a subset of the read ports coupled to the register file. However, for data access patterns such as the data access patterns characteristic of DSP functions, such restrictions may have an insignificant impact upon performance.

Abstract: A memory including first storage circuits for storing first values and second storages circuit for storing second values is provided. The first value may be retired branch prediction information, while the second value may be speculative branch prediction information. The speculative branch prediction information is updated when the corresponding instructions are fetched, and the retired branch prediction value is updated when the corresponding branch instruction is retired. The speculative branch prediction information is used to form branch predictions. Therefore, the speculatively fetched and executed branches influence subsequent branch predictions. Upon detection of a mispredicted branch or an instruction which causes an exception, the speculative branch prediction information is updated to the corresponding retired branch prediction information. An update circuit is coupled between the first and second storage circuits for transmitting the updated information upon assertion of a control signal.

Abstract: A RAM array circuit is provided which includes a memory array formed by several RAM cell columns. A particular cell within each column and row may be selected for access (either read or write) by an address decode circuit. The RAM array circuit employs a self-time column having a delay characteristic which is approximately equal to that of each of the RAM cell columns. The rising edge of a single-phase clock is used to precharge each RAM cell column as well as the self-time column. As the self-time column is precharged to a high level, the self-time control circuit disables the precharge and enables the array access for read or write. When a particular row is selected by the address decoding mechanism, the self-time column is discharged. Once the self-time column has discharged, a sense amplifier is enabled to read data from the array. Access is then disabled and precharge is again enabled upon the next rising edge of the clock.

Abstract: The present invention is an apparatus comprising first and second addressable arrays and an input for receiving address information related to the arrays. A first request line receives from a first source first request signals for access to the first and second arrays based on the address information. A second request line receives from a second source second request signals for access to the first and second arrays based on the address information. A processing circuit transmits the address information to the first and second addressable arrays in response to the first and second request signals based on a priority of the first and second request signals.

Abstract: An apparatus and method for resolving data dependencies among a plurality of instructions within a storage device, such as a reorder buffer in a superscalar computing apparatus employing pipeline instruction processing. The storage device has a read pointer, indicating a most recently-stored instruction and has a write pointer, indicating a first-stored instruction of the plurality of instructions within the storage device.

Abstract: Contention handling apparatus which receives access request signals from a number of users and processes these requests to allow controlled access to a shared resource. The contention handling apparatus includes a number of access blocks, with one of the access blocks being associated with each user. A busy line of each of the access blocks is connected to receive a busy signal; the busy signal being an access request signal from a higher priority user, thereby indicating that the shared resource is unavailable. Each access block receiving a busy signal, latches the corresponding access request signal until the busy signal is deasserted. If the busy signal and the access request signal occur at the same time, the corresponding access block generates a wait output signal. The logical sum of the wait output of an access block associated with a next higher priority user and the access request signals of all the higher priority users serves as the busy signal for one of the access blocks.

Abstract: An apparatus for controlling execution of a program of instructions in a computing device comprising an instruction fetching buffer-decoder for fetching the instructions in fetch batches and decoding the fetched instructions to generate a plurality of decoded instructions; an executing unit for executing the decoded instructions; and a storage unit including a plurality of registers for storing operand information. Each respective register includes at least one scoreboard bit indicating how the respective register is being used by the plurality of instructions; the execution unit effects execution of a specified instruction when a specified register containing operand information required by the specified instruction has a scoreboard bit having a specified value.

Abstract: An apparatus for use with a computing device for executing instructions in a logical sequence according to a control program, comprises an instruction buffer of FIFO construction serially connected to a decoder buffer also of a FIFO construction. The decoder buffer includes a number of decoder units arranged in a hierarchical manner from a lowest-significance decoder unit to a highest-significance decoder unit in order to maintain the logical sequence of the instructions. The decoder units concurrently decode instructions transmitted from the instruction buffer and concurrently determine whether a corresponding decoded instruction is ready to be sent to an instruction executing unit. Each decoder unit is capable of sending a corresponding instruction to the instruction executing unit. Instructions ready to be sent are sent to the instruction executing unit, according to the logical sequence.

Abstract: A method and apparatus is disclosed for reducing the propagation delay associated with the critical speed path of a binary logic circuit by using "multiplexing logic". More specifically, the inputs to the logic circuit are defined as either critical or non-critical inputs and the product terms are manipulated so that the non-critical inputs are mutually exclusive. The non-critical inputs are supplied to one or more first logic gate structures wherein the ultimate outputs of the first logic gate structures control multiplexer couplers. The critical speed inputs are supplied to one or more second logic gate structures wherein the ultimate outputs of the second logic gate structures are provided as the input to the multiplexer couplers.