Abstract: A processor includes a time counter and issuing instruction and executing instruction at a future time which is based on the time counter. The execution times are based on fixed latency times of instructions with exception of the load instruction which is based on the data cache hit latency time. A data cache miss causes the load instruction to fetch data from the level 2 cache wherein a time tracker unit adjusts the level 2 cache latency time based on a counter.

Abstract: A multi-chamber cartridge and a nucleic acid extraction module including the same are provided. The multi-chamber cartridge according to an aspect of the present invention may include a sample chamber including a first tube which is an elongated hollow type, a sample chamber body in which a mixing space is formed and one end of the first tube is disposed in the mixing space, a first pressure gasket which can be coupled to the inside of the first tube and is movable along the inner peripheral surface of the first tube, a first separation gasket which is disposed on one surface of the first pressure gasket, coupled to the inside of the first tube, and movable along the inner peripheral surface of the first tube, and a first plunger having one end coupled to the other surface of the first pressure gasket and pressing the first pressure gasket; and a cartridge body which includes an accommodating part in which the sample chamber is detachably accommodated.

Abstract: The air eliminator valve helps to eliminate air in the plastic resin used for composite products manufacturing. During operation, it continuously eliminates the air bubbles in the plastic resin running through the valve, and then transfers the filtered plastic resin into the mold. The design of the air eliminator valve consists of: inlet, inlet lock, air vent, upper cover, main body, ultrasonic generator, outlet lock and outlet. In which, the ultrasonic generator plays a role in generating ultrasonic waves to the plastic resin in the valve body that allows speeding up the air releasing process out the plastic resin. The air content in the valve could go out through the air vent on the upper cover, its status “open/close” is controlled by airlock with automatic response mechanism.

Abstract: Embodiments of the present disclosure support implementation of a Level-1 (L1) cache in a microprocessor based on independently accessed data and tag arrays. Presented implementations of L1 cache do not require any stall pipeline mechanism for stalling execution of instructions, leading to improved microprocessor performance. A data array in the cache is interfaced with one or more data index queues that comprise, upon occurrence of a conflict between at least one instruction requesting access to the data array and at least one other instruction that accessed the data array, at least one data index for accessing the data array associated with the at least one instruction. A tag array in the cache is interfaced with a tag queue that stores one or more tag entries associated with one or more data outputs read from the data array based on accessing the data array.

Abstract: An execution pipeline architecture of a microprocessor employs a third-pass functional unit, for example, third-level of arithmetic logic unit (ALU) or third short-latency execution unit to execute instructions with reduced complexity and area cost of out-of-order execution. The third-pass functional unit allows instructions with long latency execution to be moved into a retire queue. The retire queue further includes the third functional unit (e.g., ALU), a reservation station and a graduate buffer. Data dependencies of dependent instructions in the retire queue is handled independently from the main pipeline.

Abstract: Embodiments of the present disclosure support hardware based thread switching in a multithreading environment. The thread switching is implemented on a multithread microprocessor by utilizing thread mailbox registers and other auxiliary registers that can be pre-programmed for hardware based thread switching. A set of mailbox registers can be allocated to each thread of a plurality of threads that can be executed in the microprocessor. A mailbox register in the set of mailbox registers comprises an identifier of a next thread of the plurality of threads to which an active thread switches based on a thread switch condition further indicated in the mailbox register. The auxiliary registers in the microprocessor can be used to configure a number of threads for simultaneous execution in the microprocessor, a priority for thread switching, and to store a program counter of each thread and states of registers of each thread.

Abstract: Various embodiments of a microprocessor include a scoreboard implementation that directs the microprocessor to the location of data values. For example, the scoreboard may include individual bits that instruct the microprocessor to retrieve the data from a re-order buffer, retire queue, result bus, or register file. As a first step, the microprocessor receives an instruction indicating a process that requires data from one or more source registers. Instead of automatically retrieving the data from the register file, which is a costly process, the microprocessor may read the scoreboard to determine whether the needed data can be more cost-effectively retrieved from the re-order buffer, retire queue, or result busses. Therefore, the microprocessor can avoid costly data retrieval procedures. Additionally, the scoreboard implementation enables the microprocessor to handle limited out-of-order instructions, which improves overall performance of the microprocessor.

Abstract: Certain embodiments of the present disclosure support a method and apparatus for efficient multithreading on a single core microprocessor. Thread switching in the single core microprocessor presented herein is based on a reserved space in a memory allocated to each thread for storing and restoring of registers in a register file. The thread switching is achieved without full save and restore of the register file, and only those registers referenced in the memory are saved and restored during thread switching.

Abstract: A system, device and method of calibrating a sensor determine a sensor vector associated with a subject; process the sensor vector; determine a sensor elevation angle as a prediction of the subject's body elevation from a result of processing the sensor vector; and perform calibration using the sensor vector, sensor elevation angle, and a gravity vector.

Abstract: An execution pipeline architecture of a microprocessor employs a third-pass functional unit, for example, third-level of arithmetic logic unit (ALU) or third short-latency execution unit to execute instructions with reduced complexity and area cost of out-of-order execution. The third-pass functional unit allows instructions with long latency execution to be moved into a retire queue. The retire queue further includes the third functional unit (e.g., ALU), a reservation station and a graduate buffer. Data dependencies of dependent instructions in the retire queue is handled independently from the main pipeline.

Abstract: Various embodiments of a microprocessor include a scoreboard implementation that directs the microprocessor to the location of data values. For example, the scoreboard may include individual bits that instruct the microprocessor to retrieve the data from a re-order buffer, retire queue, result bus, or register file. As a first step, the microprocessor receives an instruction indicating a process that requires data from one or more source registers. Instead of automatically retrieving the data from the register file, which is a costly process, the microprocessor may read the scoreboard to determine whether the needed data can be more cost-effectively retrieved from the re-order buffer, retire queue, or result busses. Therefore, the microprocessor can avoid costly data retrieval procedures. Additionally, the scoreboard implementation enables the microprocessor to handle limited out-of-order instructions, which improves overall performance of the microprocessor.

Abstract: Embodiments of the present disclosure support hardware based thread switching in a multithreading environment. The tread switching is implemented on a multithread microprocessor by utilizing thread mailbox registers and other auxiliary registers that can be pre-programmed for hardware based thread switching. A set of mailbox registers can be allocated to each thread of a plurality of threads that can be executed in the microprocessor. A mailbox register in the set of mailbox registers comprises an identifier of a next thread of the plurality of threads to which an active thread switches based on a thread switch condition further indicated in the mailbox register. The auxiliary registers in the microprocessor can be used to configure a number of threads for simultaneous execution in the microprocessor, a priority for thread switching, and to store a program counter of each thread and states of registers of each thread.

Abstract: Certain embodiments of the present disclosure support a method and apparatus for efficient multithreading on a single core microprocessor. Thread switching in the single core microprocessor presented herein is based on a reserved space in a memory allocated to each thread for storing and restoring of registers in a register file. The thread switching is achieved without full save and restore of the register file, and only those registers referenced in the memory are saved and restored during thread switching.

Abstract: Embodiments of the present disclosure support implementation of a Level-1 (L1) cache in a microprocessor based on independently accessed data and tag arrays. Presented implementations of L1 cache do not require any stall pipeline mechanism for stalling execution of instructions, leading to improved microprocessor performance. A data array in the cache is interfaced with one or more data index queues that comprise, upon occurrence of a conflict between at least one instruction requesting access to the data array and at least one other instruction that accessed the data array, at least one data index for accessing the data array associated with the at least one instruction. A tag array in the cache is interfaced with a tag queue that stores one or more tag entries associated with one or more data outputs read from the data array based on accessing the data array.

Abstract: A mechanism to generate a self-clock within a synchronous processing unit of an asynchronous digital device. The self-clock is designed to match the worst-case delay of pipeline processing unit in such a way that the pipeline processing unit is operate at its own natural clock frequency and shutting off when there is no valid data to process. The synchronization logic of the processing unit consists of self-clock that generates output clock to synchronize with the internal clock edge if the processing unit is active or synchronize with the input clock edge if the processing unit is inactive.

Abstract: Apparatus for gravity flow and feeding of alloy in a casting operation has a supply vessel for holding a supply of alloy, a furnace in which the vessel is contained and in which the vessel is heatable to maintain the supply of alloy at suitable casting temperature, and a die mounted laterally outwardly from the vessel in relation to the furnace. A conduit provides communication between the vessel and the die. The apparatus further includes means for reversibly tilting an assembly including the furnace, the vessel and the die about a substantially horizontal axis to enable or prevent the flow of the alloy from the vessel to a die cavity defined by the die.

Abstract: A multi-threaded microprocessor for processing instructions in single threaded mode and multithreaded modes. The microprocessor includes instruction dependency scoreboards, instruction input coupling circuits for selectively feeding the first and second instruction dependency scoreboards; output coupling logic having first and second instruction issue outputs; first and second execute pipelines respectively coupled to the instruction issue outputs, the first execute pipeline for executing a first program thread and the second execute pipeline for executing a second program thread, independent of the first program thread; and a control logic circuit for causing dual issue of instructions from the first program thread, by the first dependency scoreboard, to both the first execute pipeline and said second execute pipeline.

Abstract: A manual or electrical toothbrush for cleaning teeth and gum pockets, the toothbrush including a neck portion; a brush head connect to one end of a neck portion; and a handle coupled to the neck portion and completely encased with gripping elements for full-gripping.

Abstract: A multi-threaded microprocessor for processing instructions in threads, including, in one embodiment, (1) at least one processor pipeline for the instructions; (2) a storage for a thread power management configuration; and (3) a power control circuit coupled to said at least one processor pipeline and responsive to said storage for thread power management configuration to control power used by different parts of the at least one processor pipeline depending on the threads, wherein said power control circuit is operable to establish different power voltages in different parts of the at least one processor pipeline depending on the threads.

Abstract: A toothbrush with secure grip and a method for brushing teeth are disclose, including picking up a toothbrush below the neck portion, a toothbrush head extending from one end of the neck portion, a round/octagon/oval shaped handle, and a grip handle extending from the other end of the neck portion, wherein the grip handle includes an array of gripping elements extending 360 degrees around the grip handle; and brushing a user's teeth and gum pockets.