Abstract: The present invention provides a method comprising the steps of: generating a second anchor on the second convolutional feature map by scaling and shifting a first anchor in the ground-truth box; generating a third convolutional feature map by convolving the second convolutional feature map by means of a second convolution; determining whether the overlap ratio between the ground-truth box and a second single anchor is greater than or equal to a reference value; generating a third anchor by scaling and shifting the second anchor having an overlap ratio that is greater than or equal to the reference value; assigning an objectivity score to the third anchor; and presenting the third anchor, which has an objectivity score that is equal to or greater than a reference value, as a proposal on the third convolutional feature map.

Abstract: The present invention provides a method comprising the steps of: generating a second anchor on the second convolutional feature map by scaling and shifting a first anchor in the ground-truth box; generating a third convolutional feature map by convolving the second convolutional feature map by means of a second convolution; determining whether the overlap ratio between the ground-truth box and a second single anchor is greater than or equal to a reference value; generating a third anchor by scaling and shifting the second anchor having an overlap ratio that is greater than or equal to the reference value; assigning an objectivity score to the third anchor; and presenting the third anchor, which has an objectivity score that is equal to or greater than a reference value, as a proposal on the third convolutional feature map.

Abstract: A processor includes allocation unit with logic to receive a logical move instruction. The logical move instruction includes a source logical register as a source parameter and a destination logical register as a destination parameter. The source logical register is assigned to a source physical register and the destination logical register is assigned to a destination physical register. The allocation unit includes logic to assign a first value of the source logical register to the destination logical register and to maintain a second value of the destination physical register before and after the assignment of the first value to the destination logical register.

Abstract: A processing device implementing stride-based translation lookaside buffer (TLB) prefetching with adaptive offset is disclosed. A processing device of the disclosure includes a data prefetcher to generate a data prefetch address based on a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, and a TLB prefetch address computation component to generate a TLB prefetch address based on the linear address, the stride, the prefetch distance, or an adaptive offset. The processing device also includes a cross page detection component to determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and cause a TLB prefetch request to be written to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) based on the data prefetch address or the TLB prefetch address.

Abstract: A processor includes allocation unit with logic to receive a logical move instruction. The logical move instruction includes a source logical register as a source parameter and a destination logical register as a destination parameter. The source logical register is assigned to a source physical register and the destination logical register is assigned to a destination physical register. The allocation unit includes logic to assign a first value of the source logical register to the destination logical register and to maintain a second value of the destination physical register before and after the assignment of the first value to the destination logical register.

Abstract: A processing device implementing stride-based translation lookaside buffer (TLB) prefetching with adaptive offset is disclosed. A processing device of the disclosure includes a data prefetcher to generate a data prefetch address based on a linear address, a stride, or a prefetch distance, the data prefetch address associated with a data prefetch request, and a TLB prefetch address computation component to generate a TLB prefetch address based on the linear address, the stride, the prefetch distance, or an adaptive offset. The processing device also includes a cross page detection component to determine that the data prefetch address or the TLB prefetch address cross a page boundary associated with the linear address, and cause a TLB prefetch request to be written to a TLB request queue, the TLB prefetch request for translation of an address of a linear page number (LPN) based on the data prefetch address or the TLB prefetch address.

Abstract: The present invention is a device to be used in emergency situations requiring floatation and rescue. An inflatable raft with a waterproof cover is connected to a telescopic shaft equipped with electric generators and a wind harnessing mechanism. The electricity, which is produced by the wind harnessing mechanism powers a motor and propeller underneath and outside the raft.