Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine a historical discharge rate (dh) from multiple discharge rates a battery of an information handling system (IHS) while the IHS operates on electrical power provided by the battery; receive a current discharge rate (dc) of the battery; determine a full charge capacity correction factor value (Cfcc) associated with the battery; determine a weighting factor (?); determine a difference between a full charge capacity value (FCC) and Cfcc; determine ?·dh; determine (1??)·dc; determine a sum of dh·? and dc·?; determine a quotient value of FCC?Cfcc and ?·dh+(1??)·dc; scale the quotient value based at least on a relative state of charge of the battery to determine an estimated time remaining for the IHS to operate on the electrical power provided by the battery; and display the estimated time remaining.

Abstract: System and method for battery runtime forecasting, including identifying a power usage of a IHS; identifying a charge profile of a battery of the IHS, the charge profile including charging levels each associated with a respective time period; determining a state of charge of the battery based on a current time; identifying power delivery capabilities of a power source providing power to the battery; generating a predicted relative state of charge (RSOC) profile of the battery based on i) the power usage of the IHS, ii) an entirety of the charge profile of the battery, iii) the state of charge of the battery, and iv) power delivery capabilities of the power source; and identifying a runtime estimate of the battery.

Abstract: A common-mode rejection receiver including a first differential amplifier arranged to receive a differential signal including receiving a positive signal of the differential signal at a first non-inverting input port and receiving a negative signal of the differential signal at a first inverting input port, and output a first differentiated signal based on a voltage differential between the positive signal and the negative signal. A clamping circuit is arranged to limit a magnitude of the first differentiated signal to a pre-determined limit. A second differential amplifier is arranged to receive the positive signal at a second inverting input port and receive the negative signal at a second non-inverting input port, and output a second differentiated signal. A matching circuit is arranged to receive the second differentiated signal output and output a matched signal. A summing circuit adds the clamped signal and matched signal and outputs a receiver output signal.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may convert first analog signals to first digital values, in which the first analog signals are proportional to current of a battery of an information handling system (IHS); convert the second analog signals to second digital values, in which the second analog signals are proportional to current from a power supply; convert the third analog signals to third digital values, in which the third analog signals are proportional to power consumption of components of the IHS and the battery; and provide a first mean digital value determined from the first digital values, a second mean value determined from the second digital values, and a third mean digital value determined from the third digital values to at least one of IHS firmware, an application, and an operating system.

Abstract: A common-mode rejection receiver including a first differential amplifier arranged to receive a differential signal including receiving a positive signal of the differential signal at a first non-inverting input port and receiving a negative signal of the differential signal at a first inverting input port, and output a first differentiated signal based on a voltage differential between the positive signal and the negative signal. A clamping circuit is arranged to limit a magnitude of the first differentiated signal to a pre-determined limit. A second differential amplifier is arranged to receive the positive signal at a second inverting input port and receive the negative signal at a second non-inverting input port, and output a second differentiated signal. A matching circuit is arranged to receive the second differentiated signal output and output a matched signal. A summing circuit adds the clamped signal and matched signal and outputs a receiver output signal.

Abstract: System and method for battery runtime forecasting, including identifying a power usage of a IHS; identifying a charge profile of a battery of the IHS, the charge profile including charging levels each associated with a respective time period; determining a state of charge of the battery based on a current time; identifying power delivery capabilities of a power source providing power to the battery; generating a predicted relative state of charge (RSOC) profile of the battery based on i) the power usage of the IHS, ii) an entirety of the charge profile of the battery, iii) the state of charge of the battery, and iv) power delivery capabilities of the power source; and identifying a runtime estimate of the battery.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may convert first analog signals to first digital values, in which the first analog signals are proportional to current of a battery of an information handling system (IHS); convert the second analog signals to second digital values, in which the second analog signals are proportional to current from a power supply; convert the third analog signals to third digital values, in which the third analog signals are proportional to power consumption of components of the IHS and the battery; and provide a first mean digital value determined from the first digital values, a second mean value determined from the second digital values, and a third mean digital value determined from the third digital values to at least one of IHS firmware, an application, and an operating system.

Abstract: In one or more embodiments, one or more systems, one or more methods, and/or one or more processes may determine a historical discharge rate (dh) from multiple discharge rates a battery of an information handling system (IHS) while the IHS operates on electrical power provided by the battery; receive a current discharge rate (dc) of the battery; determine a full charge capacity correction factor value (Cfcc) associated with the battery; determine a weighting factor (?); determine a difference between a full charge capacity value (FCC) and Cfcc; determine ?·dh; determine (1??)·dc; determine a sum of dh·? and dc·?; determine a quotient value of FCC?Cfcc and ?·dh+(1??)·dc; scale the quotient value based at least on a relative state of charge of the battery to determine an estimated time remaining for the IHS to operate on the electrical power provided by the battery; and display the estimated time remaining.

Abstract: A computing device (300) includes a storage (325) that over time is operable to include video and graphics content and the storage has a first set of instructions representing lossy video compression (130) and a second set of instructions representing lossless compression (120); and a processor (320) coupled with said storage (325), and said processor (320) operable to electronically analyze (110) at least a portion of the content for motion based on magnitudes of motion vectors and, on detection of a significant amount of motion, further operable to activate the first set of instructions (130) to compress at least the motion video, and otherwise to activate the second set of instructions representing lossless compression (120) to compress at least the graphics. Other devices, systems, and processes are disclosed.

Abstract: A video system includes a first video device. The first video device includes a video output port and an arbitrary data scrambler. The first video device transmits a video stream through the video output port. The video output port is configured to insert video timing reference values into the video stream. The arbitrary data scrambler is configured to scramble non-video data for transmission in the video stream such that unscrambled non-video data containing video timing reference values is transformed, without information loss, to scrambled non-video data containing no video timing reference values.

Abstract: A video transcoding system includes a video decoder, a video encoder, and a video interface. The video decoder is configured to decode a received video signal. The video encoder is configured to encode video data decoded from the received video signal by the video decoder. The video interface couples an output of the video decoder to an input of the video encoder and is configured to transfer video data having a first chroma subsampling ratio. The video decoder is further configured to provide video data having a second chroma subsampling ratio that includes fewer chrominance samples than the first chroma sampling ratio to the video interface, and to provide non-video information generated from decoding the received video signal to the video interface using video interface bandwidth usable based on a difference between the first chroma subsampling ratio and the second chroma subsampling ratio.

Abstract: A video system includes a first video device. The first video device includes a video output port and an arbitrary data scrambler. The first video device transmits a video stream through the video output port. The video output port is configured to insert video timing reference values into the video stream. The arbitrary data scrambler is configured to scramble non-video data for transmission in the video stream such that unscrambled non-video data containing video timing reference values is transformed, without information loss, to scrambled non-video data containing no video timing reference values.

Abstract: A video transcoding system includes a video decoder, a video encoder, and a video interface. The video decoder is configured to decode a received video signal. The video encoder is configured to encode video data decoded from the received video signal by the video decoder. The video interface couples an output of the video decoder to an input of the video encoder and is configured to transfer video data having a first chroma subsampling ratio. The video decoder is further configured to provide video data having a second chroma subsampling ratio that includes fewer chrominance samples than the first chroma sampling ratio to the video interface, and to provide non-video information generated from decoding the received video signal to the video interface using video interface bandwidth usable based on a difference between the first chroma subsampling ratio and the second chroma subsampling ratio.

Abstract: A computing device (300) includes a storage (325) that over time is operable to include video and graphics content and the storage has a first set of instructions representing lossy video compression (130) and a second set of instructions representing lossless compression (120); and a processor (320) coupled with said storage (325), and said processor (320) operable to electronically analyze (110) at least a portion of the content for motion based on magnitudes of motion vectors and, on detection of a significant amount of motion, further operable to activate the first set of instructions (130) to compress at least the motion video, and otherwise to activate the second set of instructions representing lossless compression (120) to compress at least the graphics. Other devices, systems, and processes are disclosed.

Abstract: An audio power management system for a computer eliminates audible noise associated with the cycling of power to an audio amplifier for a computer. A diode is connected between the power supply rail and the power input to the audio amplifier. One or more decoupling capacitors is provided at the power input to the audio amplifier to insulate the audio amplifier from fluctuations at the power supply. The apparatus mutes the amplifier for a brief period shortly after power becomes available and mutes the amplifier immediately when power is removed to eliminate transient noises. In one embodiment, the muting of the audio amplifier is accomplished by FET switches. In a second embodiment, the muting of the audio amplifier is accomplished by analog switches. Additionally, the audio power management system eliminates audible noise associated with the waking-up or putting the computer to sleep. The audio system asserts a speaker mute signal before power is removed from the amplifier to reduce transient conditions.

Abstract: An audio power management system for a computer to eliminate audible noise associated with the cycling of power to an audio amplifier for a computer is disclosed. A diode is connected between the power supply rail and the power input to the audio amplifier. One or more decoupling capacitors is provided at the power input to the audio amplifier to insulate the audio amplifier from fluctuations at the voltage supply rail. The apparatus also briefly mutes the amplifier when power is cycled to eliminate transient noises.Additionally, the audio power management system eliminates audible noise associated with the waking-up or putting the computer to sleep. The audio system asserts a speaker mute signal before power is removed from the amplifier to reduce transient conditions. During power up, the speaker mute signal is applied to the amplifier for a period after power has been applied to the amplifier. This control is economically accomplished using a minimal number of digital outputs.

Abstract: A clock signal is distributed over a circuit board and across a connector as a sine wave. A circuit located near the clocked circuitry converts the sine wave into a same frequency square wave for use by the clocked circuitry. The output stage of the converter circuitry provides a high output level to drive CMOS circuitry. The output transistor is pulled up to 5 volts, but the preceding transistors are pulled up to 6.3 volts so that the base to emitter drops are compensated.