Patents by Inventor Tharun Kumar

Tharun Kumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240184616
    Abstract: A thread manager creates multiple threads by to execute a simulation of subsystems of a system-on-chip on multiple processor cores in response to execution of a simulation program. The threads execute multiple cycle-accurate simulation models of the subsystems in parallel in an execution phase of each simulation cycle of a plurality of simulation cycles of the simulation. The threads update interfaces of the simulation models in an update phase of each simulation cycle of the plurality of simulation cycles.
    Type: Application
    Filed: December 6, 2022
    Publication date: June 6, 2024
    Applicant: Xilinx, Inc.
    Inventors: Tharun Kumar Ksheerasagar, Hemant Kashyap, Amit Kasat, Meghana Tripathi, Shantanu Mishra
  • Publication number: 20240070610
    Abstract: A machine-learning model (MLM) is trained to identify a given item identifier for an item and shelf dimensions of an empty space associated with the item from training images of a shelf. After training, real-time images of the shelf are provided as input to the MLM and the output provided by the MLM includes empty space identifiers, dimensions or pixel coordinates for each empty space identifier, and an item identifier for each empty space identifier. A quantity of each item identifier is determined based on known shelf dimensions that the corresponding item should occupy on a fully stocked shelf and based on the corresponding empty space dimensions for the empty space associated with the item. A real-time report is sent to store personnel and/or published on a website monitored by the store personnel. The report identifies the items, the shelves, and restocking item quantities that need restocked in the store.
    Type: Application
    Filed: August 31, 2022
    Publication date: February 29, 2024
    Inventors: Naveen Kumar Ponnaganti, Tharun Kumar Ponnaganti, Sanketh Bachoti, Akansha Prakash Chourasia, Prasanna Rajasree Mattupalli, Yaswanth Sai Velamur, Shashank Vishwanatham
  • Patent number: 11630935
    Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server.
    Type: Grant
    Filed: October 11, 2021
    Date of Patent: April 18, 2023
    Assignee: Xilinx, Inc.
    Inventors: Amit Kasat, Tharun Kumar Ksheerasagar, Hemant Kashyap, Madhusudana Reddy, Rohit Bhadana
  • Publication number: 20230113197
    Abstract: Computer-based simulation of a device under test (DUT) corresponding to a user circuit design includes providing an adapter configured to couple to the DUT during the computer-based simulation (simulation). The adapter is configured to translate incoming high-level programming language (HLPL) transactions into DUT compatible data for conveyance to the DUT and translate DUT compatible data generated by the DUT to outgoing HLPL transactions. A communication server is provided that couples to the adapter during the simulation. The communication server is configured to exchange the incoming and outgoing HLPL transactions with an entity executing external to the simulation. A communication layer client is provided that is configured to execute external to the simulation and exchange the incoming and outgoing HLPL transactions with the communication server.
    Type: Application
    Filed: October 11, 2021
    Publication date: April 13, 2023
    Applicant: Xilinx, Inc.
    Inventors: Amit Kasat, Tharun Kumar Ksheerasagar, Hemant Kashyap, Madhusudana Reddy, Rohit Bhadana
  • Publication number: 20230114858
    Abstract: Circuit design simulation and clock event reduction may include detecting, using computer hardware, a plurality of models of a circuit design driven by a clock source by parsing the circuit design. The circuit design is a mixed language circuit design including a hardware description language (HDL) model and a high-level programming language (HLPL) model. Using the computer hardware, a clock requirement for the HLPL model for a simulation of the circuit design may be determined. The clock requirement of the HLPL model differs from a clock requirement of the HDL model. Using the computer hardware, an interface of the HLPL model may be modified based on the clock requirement of the HLPL model.
    Type: Application
    Filed: October 7, 2021
    Publication date: April 13, 2023
    Applicant: Xilinx, Inc.
    Inventors: Tharun Kumar Ksheerasagar, Rohit Bhadana, Hemant Kashyap, Pratyush Ranjan
  • Publication number: 20220208320
    Abstract: A system and method for displaying physiological information is disclosed. The system includes a server to receive a first compressed data file associated with a physiological parameter of a person, decompress the first compressed data file, and analyze the decompressed data file to generate or derive a set of information associated with the person, and a client device to receive the first compressed data file, and communicate with the server to receive the set of information for display on a user interface. The server compresses the set of information to generate a second compressed data file, and sends the second compressed data file to the client device. The client device decompresses the received second compressed data and a part of the first compressed data file, and displays at least a part of the decompressed data on the user interface.
    Type: Application
    Filed: April 15, 2020
    Publication date: June 30, 2022
    Inventors: Charit Bhograj, Udayan Dasgupta, Abhinav Gujjar, Manmay Nakhashi, Suresh Velusamy, Achuth Pv, Tharun Kumar, Zainul Charbiwala
  • Patent number: 11059848
    Abstract: The present invention relates to artemisinic acid glycoconjugate compounds. More particularly, the present invention relates to a glycoconjugate compound of formula (I) and a process for the preparation of artemisinic acid glycoconjugate compound of formula (I) by using 1,3-dipolar cycloaddition chemistry starting from artemisinic acid.
    Type: Grant
    Filed: January 3, 2019
    Date of Patent: July 13, 2021
    Inventors: Asish Kumar Bhattacharya, Tharun Kumar Kotammagari, Manas Kumar Santra
  • Publication number: 20200331953
    Abstract: The present invention relates to artemisinic acid glycoconjugate compounds. More particularly, the present invention relates to a glycoconjugate compound of formula (I) and a process for the preparation of artemisinic acid glycoconjugate compound of formula (I) by using 1,3-dipolar cycloaddition chemistry starting from artemisinic acid.
    Type: Application
    Filed: January 3, 2019
    Publication date: October 22, 2020
    Inventors: Asish Kumar BHATTACHARYA, Tharun Kumar KOTAMMAGARI, Manas Kumar SANTRA