Patents by Inventor Tharun Nagulu

Tharun Nagulu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method and apparatus for reducing SAR input loading
    Patent number: 9647676
    Abstract: The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an array of MSB (most significant bit) capacitors, an array of LSB (least significant bit) capacitors, and an error correction capacitor. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A successive approximation register (SAR) state machine is coupled to the zero crossing detector and operates the charge sharing DAC in a sampling mode and a conversion mode. During the sampling mode an input voltage is provided to the array of MSB capacitors and the error correction capacitor.
    Type: Grant
    Filed: July 11, 2016
    Date of Patent: May 9, 2017
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raghu Nandan Srinivasa, Tharun Nagulu
  • Method and Apparatus for Reducing SAR Input Loading
    Publication number: 20160336952
    Abstract: The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an array of MSB (most significant bit) capacitors, an array of LSB (least significant bit) capacitors, and an error correction capacitor. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A successive approximation register (SAR) state machine is coupled to the zero crossing detector and operates the charge sharing DAC in a sampling mode and a conversion mode. During the sampling mode an input voltage is provided to the array of MSB capacitors and the error correction capacitor.
    Type: Application
    Filed: July 11, 2016
    Publication date: November 17, 2016
    Inventors: Raghu Nandan Srinivasa, Tharun Nagulu
  • Method and apparatus for reducing SAR input loading
    Patent number: 9391627
    Abstract: The disclosure provides a successive approximation register analog to digital converter (SAR ADC). The SAR ADC includes a charge sharing DAC that includes an array of MSB (most significant bit) capacitors, an array of LSB (least significant bit) capacitors, and an error correction capacitor. A zero crossing detector is coupled to the charge sharing DAC. The zero crossing detector generates a digital output. A successive approximation register (SAR) state machine is coupled to the zero crossing detector and operates the charge sharing DAC in a sampling mode and a conversion mode. During the sampling mode an input voltage is provided to the array of MSB capacitors and the error correction capacitor.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 12, 2016
    Assignee: TEXAS INSTRUMENTS INCORPORATED
    Inventors: Raghu Nandan Srinivasa, Tharun Nagulu