Abstract: A charge card apparatus and method of using the same obviates the need for the user to carry a plurality of regular charge cards on the user's person. In lieu of the plurality of charge cards, which each have magnetic strip, the user carries a charge card apparatus which has two components, i.e. a portable read/write unit and a universal blank charge card. The user records on the read/write unit, for each regular charge card, identification information along with an identification code by swiping the magnetic strip of each regular charge card in a swiping slot of the portable read/write unit. The user carries the recorded read/write unit and can log on into the read/write unit when necessary, by using a pass word/pass code.

Abstract: A PC card and corresponding WLAN system having an improved DAC operable at higher speed than heretofore achievable which exploits the sigma-delta principle in a different way. More particularly, the invention comprises a PC card (302) and corresponding WLAN system (300) that implement a digital-to-analog conversion circuit (105) including a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period.

Abstract: A digital cellular base station (22) having minimum hardware requirements readily adapted to support high speed communication is disclosed herein. It includes a digital signal processor base band processor and modulator (24), a high-speed, high resolution digital-to-analog converter (26), a RF modulator (30) and an antenna (32). An input signal couples to the digital signal base-band processing modulator (24) for processing. The high-speed, high resolution digital-to-analog converter (26) couples to receive the processed signal and converts the signal into an analog one. The high-speed, high resolution digital-to-analog converter (DAC) (26) has off-line sigma delta conversion and storage which enables it to directly generat a modulated signal at an intermediate frequency, typically on the order of 100 MHz. Incorporation of DAC (26) reduces the amount of hardware necessary for the cellular base-station (22).

Abstract: A digital-to-analog conversion circuit (105) includes a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period. An summer is coupled to each digital-to-analog converter (120, 122, 124, 126) for summing each output from each digital-to-analog converter (120, 122, 124, 126) to generate an analog output. Hereby, the digital-to-analog conversion circuit (105) according to the invention emulates a delta-sigma digital-to-analog converter having both high speed and high resolution.

Abstract: There is disclosed an integrated circuit including a phase detection circuit having an exclusive gate having first and second gate inputs for receiving first and second gate input signals. The exclusive gate provides at an output, a gate output signal that is the exclusive combination of the first and second gate input signals. A first switched resistance is coupled between a first voltage source and a common node. A second switched resistance, coupled between a second voltage source and the common node, receives the gate output signal of the exclusive gate to control the effective resistance thereof. The first and second resistances develop a signal at the common node. A comparator has a first input coupled to the common node and a second input coupled to a threshold value.

Abstract: There is disclosed an integrated circuit that includes a digital-to-analog converter having a resistor string driven by a current source. The resistor string is coupled to the current source. Intermediate taps are defined at the resistor junctions as well the resistor-current source junctions. Switching transistors are coupled between an output node and a respective intermediate tap. A selection circuit is coupled to a terminal of each switching transistor for selectively switching the transistors to a predetermined state to electrically couple the associated intermediate tap to the output node.

Abstract: A three-level digital-to-analog (D/A) converter receives digital signals, derives three-level control signals and generates analog signals. The three-level D/A converter comprises a control device for converting incoming digital signals to control signals having three levels, switches for switching responsive to these three levels to control a network of switches, and a load responsive to these switches to generate corresponding analog signals. The control device comprises a feedback control loop and a quantizer to produce the control signals having High, Medium and Low levels. The switches are preferably four switches that open and close cooperatively in response to the High, Medium and Low levels. The load generates a positive, zero or negative voltage reference in the analog signals in response to the operation of the four switches.

Abstract: The offset associated with mismatch of a pair of input devices in comparators used in applications such as flash converters is eliminated by using only one input device or transconductance circuit, time-shared between the input and reference signals. The input device converts each signal in succession into a current. A current copier stores one of these currents while the input device produces the other current, and the two currents are then compared by connecting them to a common node. The comparator includes a first switch for switching between an input and reference nodes, and an input device which receives a reference signal from the reference node during a first comparison cycle, receives an input signal from the input node during a second comparison cycle, and converts the input signal and the reference signal to input and reference currents, respectively.

Abstract: There is disclosed an integrated circuit including a resistive material runner resistor string comprising a series of resistors in which each resistor includes at least one runner direction change feature. Each resistor includes first and second contiguous elements. The junction of the first and second elements form a direction change feature such as a corner in the runner of the resistor string. Taps are positioned along the resistor string at substantially equal resistance intervals. The first and second elements may be squares of different edge dimensions. The resistor string is useful in applications such as digital-to-analog converters.

Abstract: A circuit for comparing an input signal having a first voltage to a reference signal having a second voltage to determine whether the input signal voltage is greater than or less than the reference signal voltage. In a preferred embodiment, the circuit essentially employs only four transistors (two inverters). First and second complimentary transistors are coupled in series to form the first inverter. Third and fourth complimentary transistors are coupled in series to form the second inverter. Between the first and second complimentary transistors is a first node and between the third and fourth transistors is a second node. The first and third transistors are coupled to together at a third node. The second and fourth transistors are coupled together at a fourth node. In a first phase of operation, the circuit receives the input voltage and the reference voltage.

Abstract: A circuit for conversion of an analog input signal to a digital representation of the analog signal. The circuit is typically employed in flash technology, since it is able to produce the digital representation of the analog signal faster and more efficiently than conventional flash converters. The circuit includes a plurality of resistors serially coupled between two reference voltages to form a plurality of nodes therebetween. A plurality of comparators, each having a first input coupled to one of the plurality of nodes and a second input coupled to the analog input signal. Accordingly each comparator compares the analog input signal to a voltage potential at one of the nodes to generate first and second complementary output signals at the outputs of the comparators. The complementary outputs are then applied to a decode circuit having a plurality of digital output lines and switches directly coupled to the digital output lines.

Abstract: An electronically-controlled variable propagation delay digital signal inverter comprises a digital signal inverter having an input signal port and an output signal port, and an electronically-controlled negative resistance (ECNR). The ECNR is coupled to the output port of the inverter in a configuration so as to render the propagation delay of the digital signal inverter capable of being varied by varying the resistance of the ECNR. The electronically-controlled variable propagation delay digital signal inverter may be included in a ring oscillator configuration.

Abstract: A device for digitally shaping the quantization noise of an N-bit digital signal, N being a positive integer, comprises: a register for masking out selected bits of the N-bit digital signal to produce an M-bit digital signal, M being a positive integer less than N; a digital noise-shaping coder, coupled to the register, for shaping the quantization noise of the masked out bits; and an accumulator, coupled to the register and the coder, for accumulating the digital signals received from the register and the coder. Likewise, a method of digitally shaping the quantization noise of an N-bit digital signal, N being a positive integer, comprises the steps of: masking selected bits of an N-bit digital signal to produce an M-bit digital signal, M being a positive integer less than N; digitally coding the masked bits of the N-bit digital signal to produce a B-bit digital signal, B being a positive integer less than N-M; and accumulating the M-bit digital signal and the B-bit digital signal.

Abstract: A technique for compensating for variations in a resistor set overall gain switched-capacitor circuits, such as high accuracy digital-to-analog converters. The variation in overall gain from the desired gain is due to the variation in the total capacitance of the capacitors, compared to the variation in the resistance of the resistor, in the circuit during manufacture. A bias circuit, with two reference voltage outputs, is adapted to have a capacitor and a fixed resistor vary one of the voltage references depending on the capacitance thereof. The voltage difference between the two voltage references varies the overall gain of the switched capacitor circuit to compensate for variations in the overall gain. Also, a switched-capacitor digital-to-analog converter utilizing the above technique is presented.

Abstract: A combined finite impulse response filter and digital-to-analog converter for converting sigma-delta over-sampled data into analog form. The filter removes out-of-band noise energy from the reconstructed analog signal resulting from the sigma-delta encoding process. The filter/converter is implemented in switched-capacitor technology. Further, a method of designing the optimum number of taps and the tap weight coefficients of the filter is given.

Abstract: An operational amplifier and method for making same, with predetermined common mode voltage gain, adapted to form an amplifier and a voltage regulator. The predetermined common mode voltage gain allows for substantially reduced differential mode gain and wider operating bandwidth with little distortion, compared to amplifiers and voltage regulators using operational amplifiers of the prior art. Further, examples of operational amplifiers, having the reduced differential mode gain and predetermined common mode gain, are given for implementation in CMOS and bipolar technologies.

Abstract: A novel analog comparator having cascaded gain stages powered by two buses, the voltages on which are dependent on a reference input voltage. A network, responsive to the reference input voltage, sets the voltages on the buses and isolates the buses from external power and ground to achieve high power supply and ground noise immunity. An alternative design of the network is provided which removes errors in the accuracy of the comparator resulting from differing drain-to-source voltages across the various transistors. The accuracy of the comparator is then dependent on the accuracy of matching predetermined ratios of the sizes of the transistors.

Abstract: An improved CMOS bandgap voltage reference in which a magnified current derived from a thermal voltage reference produces a voltage drop across a resistor. The resistor in turn couples to a single bipolar transistor which is part of the thermal voltage reference. The bandgap voltage is the sum of the voltage across the resistor and the voltage across the bipolar transistor. In addition, the immunity of a bandgap voltage reference to variations in power supply variations is improved by having a differential amplifier sense the voltages at the control current input and the output of a current mirror in the thermal voltage reference portion of the bandgap voltage reference and adjusting the power supply voltage to the thermal voltage reference until the sensed voltages are substantially the same.

Abstract: A novel fully differential analog comparator having cascaded gain stages powered by two buses. The two buses are powered by a current source and a variable gain current mirror responsive to the current source. The current source and the current mirror isolate the buses from external power and ground to achieve high power supply noise immunity. True and complementary outputs of the comparator are provided having an adjustable output common mode voltage to optimize the driving of subsequent logic gates responsive to the comparator.

Abstract: A voltage generator circuit consists essentially of two separate groups of serially connected semiconductor junctions with one group having one more junction than the other, two groups of constant current sources, and a differential operational amplifier. The circuit generates a reference voltage which in one embodiment is close to the bandgap voltage of silicon and is essentially constant over an operating temperature range of 25-85 degrees C. and does not require the trimming (adjusting) of resistor values. This circuit is particularly useful in CMOS CODECs. The circuit is designed such that the input offset voltage of an operational amplifier is not multiplied by the gain of the amplifier.