Abstract: A wireless communications apparatus and corresponding system having an improved DAC operable at higher speed than heretofore achievable which exploits the sigma-delta principle in a different way. More particularly, the invention comprises a wireless user terminal (302) and corresponding system (300) that implement a digital-to-analog conversion circuit (105) including a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period.

Abstract: Processing signals to record media information includes receiving an analog signal at an analog-to-digital converter, where the analog signal includes media information. The analog-to-digital converter converts the analog signal to a corresponding digital signal, where the digital signal includes a first sequence having a first number of bits. A sigma-delta converter processes the digital signal according to a sigma-delta conversion, where the processed digital signal includes a second sequence having a second number of bits, and where the second number of bits is lower than the first number of bits. The processed digital signal is stored in a digital format in a medium in order to record the media information.

Abstract: Processing signals to record media information includes receiving an analog signal at an analog-to-digital converter, where the analog signal includes media information. The analog-to-digital converter converts the analog signal to a corresponding digital signal, where the digital signal includes a first sequence having a first number of bits. A sigma-delta converter processes the digital signal according to a sigma-delta conversion, where the processed digital signal includes a second sequence having a second number of bits, and where the second number of bits is lower than the first number of bits. The processed digital signal is stored in a digital format in a medium in order to record the media information.

Abstract: A wireless local loop apparatus and corresponding system having an improved DAC operable at higher speed than heretofore achievable which exploits the sigma-delta principle in a different way. More particularly, the invention comprises a wireless local loop terminal (302) and corresponding system (300) that implement a digital-to-analog conversion circuit (105) including a storage means (110), such as a read only memory, for storing delta-sigma analog sequences corresponding to all possible values of a digital input (106) coupled to a plurality of one-bit digital to analog converters (120, 122, 124, 126). Each of the digital-to-analog converters (120, 122, 124, 126) are clocked by multi-phase clocks, such that each phase applied to each one of the digital-to-analog converters (120, 122, 124, 126) is delayed with respect to one another by the oversampling period.

Abstract: There is disclosed an integrated circuit including a resistor string comprising a plurality of resistors. The resistor string includes a first array of resistors for determining a predetermined number, M, of most significant bits, and a second array of resistors for determining a predetermined number, L, of least significant bits. Each of the first and second arrays of resistors define intermediate taps. First and second arrays of switching transistors are coupled to the respective taps in respective first and second arrays of resistors. Switches in the first array of switching transistors are coupled between a respective intermediate tap in the first array of resistors and a first output node. Transistors in a second array of switching transistors are coupled between a respective intermediate tap in the second array of resistors and a second output node.

Abstract: There is disclosed an integrated circuit in accordance with an illustrative embodiment of the present invention, method of operating a digital converter includes a capacitor on which a sampled analog signal is stored. The capacitor has a first element and a second element. The second element is capable of being referenced to more than one potential. The analog-to-digital converter includes a voltage gradient and a comparator for comparing the sampled analog signal to selected voltages of the voltage gradient to indicate which is larger. Each of the voltages developed along the voltage gradient corresponds to a digital code representative of the voltage.

Abstract: An integrated circuit for converting an analog signal to a digital signal includes a resistor string comprised of a plurality of serially coupled resistors coupled between a high voltage reference and a low voltage reference. Intermediate taps are defined at the junctions of the resistors in the resistor string. At least one comparator has first and second inputs and an output. The first input of the comparator is capable of being selectively coupled to preselected ones of the intermediate taps. The second input is capable of being switched between an unknown analog input in conversion mode and a predetermined tap that provides a nominal voltage at the second input in calibration mode. A selection circuit for sequencing through the preselected ones of the intermediate taps selects one of the preselected ones of the intermediate taps as a selected tap for compensating for the offset of the at least one comparator. The selection circuit stores the selected tap for subsequent use during operation of the circuit.

Abstract: An analog-to-digital converter includes first current sources, second current sources, current regulators, and conductive channels, with each conductive channel coupled to a respective first current source, second current source, and current regulator. An analog input is split into the first current sources. Each second current source is associated with a unique reference current. At each channel where the first current source couples a larger current than the reference current, the current regulator couples a difference current to allow the second current source to couple the reference current. Alternatively, at each channel where the first current source couples a smaller current than the reference current, the current regulator does not couple a difference current, and the second current source couples the same current as the first current source.