Abstract: The subject specification comprises techniques employing multi-stage multi-layer switches for packet switching using fully shared buffers with a scalable switch fabric. A switch component includes a set of input modules (IMs) of switches that receive packets and are associated with a set of central modules (CMs) of switches that are associated with a set of memories. The switch component includes a second set of CMs associated with the set of memories, the second set of CMs being associated with a set of output modules (OMs) that can provide packets as output. A switch management component controls switching of the packets between the IMs and first set of CMs to the memories during a first switching phase, and switching of the packets from the memories to the second set of CMs to the OMs for output during a second switching phase, based on a defined scheduling algorithm.

Abstract: Distributive content delivery techniques are applied in a content delivery system. A content delivery overlay is generated as a function of delay times, bandwidth requirements, and throughput of a network. Helpers are added to the content delivery network as a function of delay times, bandwidth requirements, and throughput. Further, content can be transmitted without exchanging buffermaps or waiting for whole packets to be transmitted.

Abstract: Provided herein are fluorescent bioprobes comprising fluorogens that exhibit aggregation-induced emission (AIE) labeled on biomolecules. The present subject matter relates to a fluorescent bioprobe comprising one or more fluorogen labeled on chitosan. The present subject matter is also directed to methods of preparing the fluorescent bioprobes, methods of labeling and detecting DNA and/or proteins with the fluorescent bioprobe, and methods of cell imaging including live cell tracking.

Abstract: Described herein is a microchannel that is formed beneath and parallel to a surface of a silicon substrate. Silicon migration technology is utilized to form a microchannel that is buried beneath the surface of the silicon substrate. Etching opens at least one end of the microchannel. Oxidization is utilized through the open end of the microchannel to facilitate a controlled diameter of the microchannel.

Abstract: Network on Chips (NoC)s with a bufferless and nonblocking architecture are described. Core processors are communicatively coupled together on a substrate with a set of routing nodes based on nonblocking process. A network component routes data packets through the routing nodes and the core processors via communication links. A bufferless cross bar switch facilitates the communication of the data packets and/or path setup packets through the communication links among source processors and destination processors. The communication links include one or more channels, in which a channel comprises a data sub-channel, an acknowledgement sub-channel and a release sub-channel.