Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

Abstract: After planarization of a gate level dielectric layer, a dummy structure is removed to form a recess. A first conductive material layer and an amorphous metal oxide are deposited into the recess area. A second conduct material layer fills the recess. After planarization, an electrical antifuse is formed within the filled recess area, which includes a first conductive material portion, an amorphous metal oxide portion, and a second conductive material portion. To program the electrical antifuse, current is passed between the two terminals in the pair of the conductive contacts to transform the amorphous metal oxide portion into a crystallized metal oxide portion, which has a lower resistance. A sensing circuit determines whether the metal oxide portion is in an amorphous state (high resistance state) or in a crystalline state (low resistance state).

Abstract: A one-time programmable field effect transistor (FET) e-fuse has a silicided gate connected to the drain while the source is grounded. A voltage stimulus applied to the drain forces current to flow through the channel coupling the drain to the source. The magnitude of the current exceeding the threshold current density initiates electromigration of the source/drain silicide into the channel region, such that the source/drain of the FET is shorted to the substrate after programming. Under these constraints, the fuse device conducts current even when the transistor is in the off-state. The MOSFET e-fuse preferably uses a minimum channel length NFET/PFET and scales down its dimensions to conform to those allowed by the technology.

Abstract: A one-time programmable field effect transistor (FET) e-fuse has a silicided gate connected to the drain while the source is grounded. A voltage stimulus applied to the drain forces current to flow through the channel coupling the drain to the source. The magnitude of the current exceeding the threshold current density initiates electromigration of the source/drain silicide into the channel region, such that the source/drain of the FET is shorted to the substrate after programming. Under these constraints, the fuse device conducts current even when the transistor is in the off-state. The MOSFET e-fuse preferably uses a minimum channel length NFET/PFET and scales down its dimensions to conform to those allowed by the technology.

Abstract: In an integrated circuit having an on-chip power supply, a voltage maintenance circuit includes a decoupling capacitor connected between the output node and ground, a supplementary capacitor connected between a supplementary node and ground and a controllable transistor connected between the two capacitor nodes, so that when the output voltage drops below a threshold a reference circuit turns on the controllable transistor, thereby supplying extra charge to the output node and restoring it to its design voltage more quickly than the power supply could.

Abstract: A trench SOI structure is described. The structure is useful, for instance in the fabrication of DRAM cells. The structure can be fabricated by extending the conventional substrate plate trench cell. The SOI cell eliminates the parasitic trench sidewall leakage, reduces soft errors, eliminates well to substrate leakage, in addition to all the other advantages of SOI devices.

Abstract: The invention is a high density cross point folded bitline trench DRAM cell with a cell area of only 4 lithographic squares. The access device (transfer device) is vertically disposed on the side of a trench. In a preferred embodiment, poly spacer wordlines are used. The width of the wordlines can be increased, without increasing the cell area, by increasing the depth of the shallow trench. This will result in faster cell access due to the lower RC time constant of the wordline. The diffusion contact to the storage node, as well as the access device, is placed on one side of the trench to minimize the interaction between adjacent nodes, especially with scaling. The cell has a simple topography, and uses only one level of bitline wiring.

Abstract: A method for making high capacitance multi-level storage node contact is proposed for high density SRAMs. The proposed contact connects several poly levels to diffusion and to a trench capacitor, in one contact. The high storage node capacitance provided by the trench capacitor substantially reduces the soft error rate probability of the cell. The use of a single contact to connect several levels reduces the area. The contact preferably uses TiN as a barrier layer to reduce dopant diffusion between different poly layers.

Abstract: Methods for fabricating low leakage trenches for Dynamic Random Access Memory (DRAM) cells and the devices formed thereby are disclosed. In one embodiment of the present invention, the method includes forming a diffusion ring surrounding an upper portion of the trench. In another embodiment, a portion of the diffusion ring extends to the surface of a substrate. The diffusion ring can be formed by outdiffusing a dopant from a doped material deposited within the trench. In a further embodiment, the present method includes forming an insulating ring surrounding an upper portion of the trench. The insulating ring can be formed by thermal oxidation or by etching a sidewall shallow trench and depositing an insulating material therein. In another embodiment, a portion of the insulating ring extends to the surface of the substrate.

Abstract: A high capacitance multi-level storage node contact is proposed for high density SRAMs. The proposed contact connects several poly levels to diffusion and to a trench capacitor, in one contact. The high storage node capacitance provided by the trench capacitor substantially reduces the soft error rate probability of the cell. The use of a single contact to connect several levels reduces the area. The contact preferably uses TiN as a barrier layer to reduce dopant diffusion between different poly layers.

Abstract: Low leakage trenches for Dynamic Random Access Memory (DRAM) cells and the devices formed thereby are disclosed. In one embodiment of the present invention, [the method includes forming] a diffusion ring is surrounding an upper portion of the trench. In another embodiment, a portion of the diffusion ring extends to the surface of a substrate. The diffusion ring can be formed by outdiffusing a dopant from a doped material deposited within the trench. In a further embodiment, the present [method] invention includes [forming] an insulating ring surrounding an upper portion of the trench. The insulating ring can be formed by thermal oxidation or by etching a sidewall shallow trench and depositing an insulating material therein. In another embodiment, a portion of the insulating ring extends to the surface of the substrate.

Abstract: A trench capacitor and a method of forming same within an integrated circuit. The capacitor includes a first plate electrode having a surface area comprised of an inner surface area of the trench and an outer surface area of an upstanding pillar structure that is formed within the trench and which extends upwardly from a bottom surface thereof. The pillar structure is physically and electrically contiguous with the semiconductor substrate and has the same type of electrical conductivity. The capacitor further includes a second plate electrode comprised of a region of electrically conductive material that substantially fills a volume of the trench. The capacitor further includes a thin layer of dielectric material interposed between the first plate electrode and the second plate electrode. The second plate electrode is conductively coupled to a planar access device through a conductive, self-aligned surface strap.

Abstract: A self-timed precharge circuit for a memory array consisting of an X-line complement circuit connected to the outputs of a plurality of falling edge detectors, and a precharge generator circuit connected to the output of the X-line complement circuit. Each falling edge detector is connected to a separate wordline (WL, WL+1, . . . WL+N) of the system memory array. In operation, the precharge generator circuit is triggered with a signal on the output lead from a falling edge detector which is activated when the selected wordline (WL, WL+1, . . . WL+N) connected thereto resets.

Abstract: A decoder/driver circuit for a semiconductor momory having a A1 to AN (true) and A1 to AN (complement) address lines for receiving A1 to AN address bit signals thereon from internal address buffers. A .PHI.PC line is included for receiving a .PHI.PC precharge clock signal thereon and a .PHI.R line is provided for receiving a .PHI.R reset clock signal thereon. The decoder/driver circuit includes a NOR decoder means having a plurality of transistor switching devices connected to A1 to AN-1 or A1 to AN-1 of the true and complement address lines for the AN to AN-1 address bits for producing a high or low level signal on a decoder output node depending on the address bits state. The decoder/driver circuit further includes a selection means having a plurality of transistor devices connected to the output node of the decoder to produce a first selection signal when the decoder output node and the AN line is high and a second selection signal when the decoder output node and the AN line is high.

Abstract: Josephson solitons are steered along selected paths in response to applied control signals, the output path chosen being dependent solely upon the presence and absence of these control signals. An input Josephson transmission line is provided along which the Josephson soliton travels. This input line intersects with two output Josephson transmission lines. Bias currents of opposite polarity in the output transmission lines are used to steer the soliton into a selected one of the output lines. At the intersection of the input line and the output lines an isolating resistor is located. This resistor dissipates the anti-soliton created at the intersection and provides isolation between the input and the output of the device. In a preferred embodiment, one electrode of the input and output Josephson transmission lines can be comprised of a common superconductor and the isolating resistor can be located between the other electrodes of the output transmission line.