Patents by Inventor Thekkemadathil Velayudhan Rajeevakumar

Thekkemadathil Velayudhan Rajeevakumar has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5930107
    Abstract: A dual trench structure for a high density trench DRAM. The dual trench structure, each of which can reside in part under the access device of a respective cell, does not require the use of expensive selective epi growth techniques. A sub-minimum lithographic trench opening can be used (1) to improve the cell area, (2) to increase the device length, and (3) to improve the margin of diffusion straps. Acceptable trench capacitance for the cells formed in a single opening can be achieved either by using thin capacitor dielectric, or by expanding the trenches laterally under the devices.
    Type: Grant
    Filed: May 15, 1997
    Date of Patent: July 27, 1999
    Assignee: International Business Machines Corporation
    Inventor: Thekkemadathil Velayudhan Rajeevakumar
  • Patent number: 5869868
    Abstract: A trench SOI structure is described. The structure is useful, for instance in the fabrication of DRAM cells. The structure can be fabricated by extending the conventional substrate plate trench cell. The SOI cell eliminates the parasitic trench sidewall leakage, reduces soft error, eliminates well to substrate leakage, in addition to all the other advantages of SOI devices.
    Type: Grant
    Filed: June 26, 1996
    Date of Patent: February 9, 1999
    Assignee: International Business Machines Corporation
    Inventor: Thekkemadathil Velayudhan Rajeevakumar
  • Patent number: 5811993
    Abstract: A FET band-gap reference generating circuit having a two-branch differential amplifier with a saturation state FETs for equal branch current, independent of power supply voltage, with a feedback connection to a reference FET in one branch, for driving the steady state output to the threshold voltage of the reference FET, also independent of the power supply voltage. A multistage circuit connects a divided down output of a first FET band-gap reference generating circuit to a current bias terminal of similar second FET based differential amplifier so that the steady state output of the second amplifier is equal to the sum of the divided down output and a threshold voltage of a second reference FET in the second amplifier.
    Type: Grant
    Filed: October 4, 1996
    Date of Patent: September 22, 1998
    Assignee: International Business Machines Corporation
    Inventors: Robert Heath Dennard, Thekkemadathil Velayudhan Rajeevakumar
  • Patent number: 5692281
    Abstract: A dual trench structure for a high density trench DRAM. The dual trench structure, each of which can reside in part under the access device of a respective cell, does not require the use of expensive selective epi growth techniques. A sub-minimum lithographic trench opening can be used (1) to improve the cell area, (2) to increase the device length, and (3) to improve the margin of diffusion straps. Acceptable trench capacitance for the cells formed in a single opening can be achieved either by using thin capacitor dielectric, or by expanding the trenches laterally under the devices.
    Type: Grant
    Filed: January 16, 1996
    Date of Patent: December 2, 1997
    Assignee: International Business Machines Corporation
    Inventor: Thekkemadathil Velayudhan Rajeevakumar
  • Patent number: 5658816
    Abstract: A trench structure for a high density trench DRAM cell is proposed. The proposed trench structure, which resides in part under the access device of the cell, does not require the use of expensive selective epi growth techniques. For the proposed cell, sub-minimum lithographic trench opening can be used (1) to improve the cell area, (2) to increase the device length, and (3) to improve the margin of diffusion strap. For the proposed cell structure, trench capacitance can be significantly increased without etching deeper trenches, or using thinner capacitor dielectric, by expanding the trench laterally under the device.
    Type: Grant
    Filed: February 27, 1995
    Date of Patent: August 19, 1997
    Assignee: International Business Machines Corporation
    Inventor: Thekkemadathil Velayudhan Rajeevakumar