Patents by Inventor Thelma C. Taylor

Thelma C. Taylor has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug
    Patent number: 6596563
    Abstract: In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.
    Type: Grant
    Filed: March 4, 2002
    Date of Patent: July 22, 2003
    Assignee: Sun Microsystems, Inc.
    Inventors: Xuejun Yuan, Xiaowei Jin, Rambabu Pyapali, Raymond A. Heald, James M. Kaku, Helen Dunn, Thelma C. Taylor, Peter F. Lai, Aharon Ostrer
  • Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug
    Publication number: 20020096774
    Abstract: In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design.
    Type: Application
    Filed: March 4, 2002
    Publication date: July 25, 2002
    Inventors: Xuejun Yuan, Xiaowei Jin, Rambabu Pyapali, Raymond A. Heald, James M. Kaku, Helen M. Dunn, Thelma C. Taylor, Peter F. Lai, Aharon Ostrer
  • Method for double-layer implementation of metal options in an integrated chip for efficient silicon debug
    Patent number: 6396149
    Abstract: In one aspect of the present invention, a method provides a connecting path diversion through an upper layer of an integrated circuit by alteration of a connecting path through a lower layer of the integrated circuit. This method enables a circuit path in an integrated circuit to be modified in an accessible layer for testing before the modified circuit path is incorporated in a redesigned integrated circuit design. In another aspect of the present invention, a modified multi-layer integrated circuit chip includes a connecting path formed in a lower layer and a substitute connecting path that is etched in the lower layer. Subsequently, the connecting path formed in the lower layer may be severed.
    Type: Grant
    Filed: June 13, 2000
    Date of Patent: May 28, 2002
    Assignee: Sun Microsystems, Inc.
    Inventors: Xuejun Yuan, Xiaowei Jin, Rambabu Pyapali, Raymond A. Heald, James M. Kaku, Helen Dunn, Thelma C. Taylor, Peter F. Lai, Aharon Ostrer