Abstract: A radio frequency front end module (FEM) coupled to a radio frequency transceiver circuit and includes a first port coupled to a sending branch and a receiving branch through a switching system, and a second port coupled to the sending branch and the receiving branch through the switching system. The first port supports signal transmission of a first frequency band, and the second port supports signal transmission of a second frequency band. The receiving branch supports receiving processing of signals of the first frequency band and the second frequency band. The sending branch supports sending processing of signals of the first frequency band and the second frequency band. The switching module is configured to selectively transmit a signal either processed by the sending branch to the first port or the second port, or received by the first port or a signal received by the second port to the receiving branch.

Abstract: The present disclosure relates to the field of communication technologies, and provide a near-field communication (NFC) chip, a phase synchronization method, and an electronic device, to quickly synchronize a transmitted signal of an NFC card device with a carrier of an NFC card reader. The NFC chip includes a processing circuit configured to: determine a first carrier frequency offset between a local clock signal and a carrier clock signal, and generate a first frequency control word based on the first carrier frequency offset. The carrier clock signal is determined based on a received signal received by the NFC chip. The NFC chip further includes a phase-locked loop configured to generate a first clock signal based on the local clock signal and the first frequency control word.

Abstract: A multi-phase clock generation circuit is configured to generate a multi-phase non-overlapping clock signal and includes a loop structure, where input ends and output ends of a plurality of logic gates are electrically coupled head to tail to form the loop structure; and a plurality of latches configured to latch signals at the input ends of the logic gates. The multi-phase clock generation circuit performs a logical operation based on selection signals and clock signals that are received at the logic gates, latches data of upper-stage logic gates that is received at logic gates in a loop through the latches, and outputs multi-phase non-overlapping clock signals through the output ends of the logic gates.

Abstract: Embodiments of this application provide a short-range communications apparatus, a chip, and a control method. The apparatus includes: a gain unit, coupled to an antenna; a first radio frequency RF receive channel, coupled to the gain unit; a first baseband processor, coupled to the first RF receive channel, and configured to receive a first signal from the antenna through the first RF receive channel; a second RF receive channel, coupled to the gain unit; and a second baseband processor, coupled to the second RF receive channel, and configured to receive a second signal from the antenna through the second RF receive channel.

Abstract: A time-to-digital converter (TDC) is disclosed, which comprises a ring oscillator module and a digital error correction module. The ring oscillator module is configured to receive a sampling signal, an addressing signal, and a preset signal, and includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters for generating a first output signal; a counter clock generator configured to generate first and second clock signals; first and second counters configured to respectively generate first and second counter output signals; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals. The digital error correction module is arranged to process the first, second and third output signals for generating a digital signal.

Abstract: A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit is disclosed, which comprises: a DTC error compensator arranged to receive a phase offset signal being a processed output from a time-to-digital converter (TDC) circuit, the phase offset signal includes a DTC error corresponding to a phase difference between a reference clock signal processed by a DTC circuit and a feedback clock signal derived from an output signal of the ADPLL circuit. The compensator is arranged to process the phase offset signal for generating a digital signal representative of the DTC error, which is provided as an output signal. Also, the output signal is arranged to be subtracted from the phase offset signal to obtain a phase rectified signal of the phase offset signal.

Abstract: A digital-to-time converter (DTC) assisted all digital phase locked loop (ADPLL) circuit is disclosed, which comprises: a DTC error compensator arranged to receive a phase offset signal being a processed output from a time-to-digital converter (TDC) circuit, the phase offset signal includes a DTC error corresponding to a phase difference between a reference clock signal processed by a DTC circuit and a feedback clock signal derived from an output signal of the ADPLL circuit. The compensator is arranged to process the phase offset signal for generating a digital signal representative of the DTC error, which is provided as an output signal. Also, the output signal is arranged to be subtracted from the phase offset signal to obtain a phase rectified signal of the phase offset signal.

Abstract: A time-to-digital converter (TDC) is disclosed, which comprises a ring oscillator module and a digital error correction module. The ring oscillator module is configured to receive a sampling signal, an addressing signal, and a preset signal, and includes: a ring oscillator arranged with a plurality of inverters; a phase sampler configured to sample phase signals generated by the inverters for generating a first output signal; a counter clock generator configured to generate first and second clock signals; first and second counters configured to respectively generate first and second counter output signals; and a data sampler configured to sample the first and second counter output signals to respectively generate second and third output signals. The digital error correction module is arranged to process the first, second and third output signals for generating a digital signal.

Abstract: The embodiments of the invention provide a method and device for radio frequency (RF) limiting. The device for RF limiting comprises: an analog limiter configured to limit a voltage of a RF input to a predetermined safe range during power-off or power-up until a disable control signal is received from the digital controller, a sensing circuit configured to sense a plurality of shunting currents provided by the analog limiter in sequence to determine a value of each bit of a preset current sensing code and sense the limiting voltage, a digital controller configured to control the digital limiter to perform RF limiting function based on the value of each bit of the preset current sensing code, and control the analog limiter to stop limiting the voltage of the RF input if the limiting voltage is within a predetermined acceptable voltage range.

Abstract: A near field communication (NFC) device configured to use in preparing a carrier signal for active load modulation supporting both synchronous and asynchronous transmissions. The NFC device comprises a local clock generator for generating a reference clock signal (REF_CLK), a clock extractor for recovering a clock signal (EXT_CLK) generated by an NFC initiator device, a frequency tracking module (FTM) for performing a frequency tracking operation based on an input clock signal (REF_CLK or EXT_CLK) to produce a FTM output with its frequency aligned with the input clock signal, and a phase tracking module (PTM) for performing a phase tracking operation on the FTM output based on EXT_CLK to produce a PTM output with its phase aligned with EXT_CLK.

Abstract: Embodiments of the invention provide a system and method for direct RF sampling a Near Field Communication (NFC) receiver at a rate higher than the carrier frequency by reducing and shifting requirements at a front end analog module to a digital module.

Abstract: Embodiments of the invention provide a system and method for direct RF sampling a Near Field Communication (NFC) receiver at a rate higher than the carrier frequency by reducing and shifting requirements at a front end analog module to a digital module.

Abstract: A near field communication (NFC) device configured to use in preparing a carrier signal for active load modulation supporting both synchronous and asynchronous transmissions. The NFC device comprises a local clock generator for generating a reference clock signal (REF_CLK), a clock extractor for recovering a clock signal (EXT_CLK) generated by an NFC initiator device, a frequency tracking module (FTM) for performing a frequency tracking operation based on an input clock signal (REF_CLK or EXT_CLK) to produce a FTM output with its frequency aligned with the input clock signal, and a phase tracking module (PTM) for performing a phase tracking operation on the FTM output based on EXT_CLK to produce a PTM output with its phase aligned with EXT_CLK.

Abstract: The invention provides a method and device for Radio Frequency (RF) limiting. The device for RF limiting comprises: an Analog Limiter configured to limit a voltage of a RF input to a predetermined safe range during power-off or power-up until a disable control signal is received from the Digital Controller, a Sensing Circuit configured to sense a plurality of shunting currents provided by the Analog Limiter in sequence to determine a value of each bit of a preset current sensing code and sense the limiting voltage, a Digital Controller configured to control the Digital Limiter to perform RF limiting function based on the value of each bit of the preset current sensing code, and control the Analog Limiter to stop limiting the voltage of the RF input if the limiting voltage is within a predetermined acceptable voltage range.

Abstract: An automatic gain control system comprises a number of variable gain stages connected in series and a number of sensors, the input of each sensor being connected to a respective output of the variable gain stages. The input of an analogue-to-digital converter is connected to the output of one of the variable gain stages. The input of a control unit is connected to the outputs of the sensors and to the output of the analogue-to-digital converter. The input of a digital-to-analogue converter is connected to the output of the control unit, and the control inputs of each of the variable gain stages is connected to an output of the digital-to-analogue converter. The outputs of the digital-to-analogue converter are used to control the gains of the variable gain stages. Also disclosed is a method for automatically controlling gain in a receiver system.

Abstract: A differential detector is disclosed which comprises: a frequency converter (230) arranged to convert an input signal into demodulated baseband signals; samplers (217, 218) arranged to sample said demodulated baseband signals at a sampling frequency to provide sampled signals; a demodulator (231) arranged to demodulate the sampled signals to provide a demodulated signal; and a data slicer (310) arranged to sense an envelope of the demodulated signal to provide an envelope signal and a comparator (224) arranged provide an output signal dependent upon the demodulated signal and the envelope signal.

Abstract: A digital receiver, comprising: a frequency converter (100, 101, 102, 103, 104, 105) arranged to convert a received signal into baseband signals; delay units (106, 107) arranged to delay the baseband signals to provide delayed signals; normalizing means (108) arranged to truncate the baseband signals and the delayed signals to a predetermined length and provide normalized signals; a demodulator (109) arranged to demodulate the normalized signals and provide a demodulated signal; and frequency offset sensing means (110) arranged to sense an envelope of the demodulated signal to provide an offset signal indicative of a frequency offset of the received signal.

Abstract: A signal processing circuit arranged to be used in a frequency modulated signal receiver is disclosed which includes a complex filter 105-110 connected to analog to digital converter 112, the filter having first 105-108 and second 109,110 complex filter stages and a voltage limiter 108 disposed between the stages. The circuit is of particular applicability for use in a Bluetooth receiver.