Abstract: Described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. The tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an HLS-efficient representation of program code for input into high-level synthesis tools.

Abstract: Described herein is a technique to enable the construction of hierarchical clock gating architectures via e-graph rewriting. Automated clock gating relies on multiplexor (mux) tree analysis and constructs simple register enable signals. A framework is provided to detect non-mux based opportunities and construct more complex clock gating signals.

Abstract: Examples relate to an apparatus, a device, a method, and a computer program for generating a circuit design of polynomial interpolation hardware. The apparatus comprises processing circuitry configured to sub-divide the range of input values of the polynomial interpolation hardware into a plurality of regions, determine, for each region of the plurality of regions, a set of polynomial approximations that are suitable in view of a desired accuracy of the polynomial interpolation hardware, remove, based on one or more user-defined objectives, polynomial approximations from the respective sets of polynomial approximations, and generate the circuit design of the polynomial interpolation hardware based on one polynomial approximation per region remaining in the respective sets of polynomial approximations after the iterative removal of polynomial approximations.

Abstract: Described herein is a technique for automatic generation of optimized RTL via redundant code removal. By automatically introducing local mutations into the original RTL and using equivalence checking tools to confirm that the functionality it is not affected, optimized RTL can be produced automatically without requiring human intervention.

Abstract: An apparatus to facilitate floating point compliance verification is disclosed. The apparatus includes processing circuitry to load a design under test (DUT) into a formal equivalence checking tool; define a floating point (FP) component of interest of the DUT; based on the DUT and a reference specification, produce a set of verification properties for the FP component of interest, wherein the set of verification properties is generated for each flag having no freedom, each flag having freedom, for output data having multiple allowable outputs, and for output data having infinitely precise results; check the generated set of verification properties at the formal equivalence checking tool using the DUT and the reference specification; and generate a verification properties report at a conclusion of running the formal equivalence checking tool to detail the set of verification properties.

Abstract: An apparatus to facilitate accelerating mutation testing for simulation and formal verification is disclosed. The apparatus includes processing circuitry to define a set of mutations and a set of verification properties for an original design under test (DUT); utilize a conditional input bit to conditionally activate the set of mutations in the original DUT; generate a conditional DUT comprising the original DUT having the conditional input bit applied to the set of mutations; for each verification property, inspect a query associated with the verification property and the conditional DUT to determine whether the verification property has at least one mutation of the set of mutations that has a corresponding conditional input bit that is present; and run a verification sign-off tool that executes the verification properties that are determined to have the at least one mutation of the set of mutations with the corresponding conditional input bit that is present.

Abstract: One embodiment provides a graphics processor comprising a memory interface and a graphics core cluster including a plurality of graphics cores and tensor processing circuitry. The tensor processing circuitry includes a local memory, a tensor accelerator coupled with the local memory, the tensor accelerator configured to perform a matrix multiply and accumulate operation, and a tensor data movement accelerator configured to asynchronously transfer tensor data between a global memory coupled to the memory interface and the local memory. The tensor data movement accelerator includes circuitry configured to translate the tensor data from a first tensor format to a second tensor format.

Abstract: An apparatus to facilitate summarizing stimulus space via clustering and stochastic processes is disclosed. The apparatus includes processing circuitry to: receive an original set of stimuli input data, the stimuli input data comprises variables for input to an electronic circuit simulator to check an integrity of integrated circuit designs and to predict integrated circuit behavior; apply a clustering algorithm to the original set to determine k subsets of the original set; define, for each subset of the k subsets, a random variable per subset in accordance with a distribution corresponding to the subset; compute inter-cluster transition probabilities between the k subsets; sample, in accordance with the inter-cluster transition probabilities, a reduced set of the stimuli input data from the k subsets of the original set; and utilize the reduced set as a smaller representative set of the stimuli input data for input to the electronic circuit simulator.

Abstract: One embodiment provides a graphics processor comprising a memory interface and a processing resource coupled with the memory interface. The processing resource including a mixed format functional unit configured to receive an integer input and a floating-point input, perform a fused format conversion multiply operation on the integer input and the floating-point input to generate a floating-point result, and output the floating-point result.

Abstract: One embodiment provides a graphics processor comprising a memory interface and a processing resource coupled with the memory interface. The processing resource including circuitry configured to perform an operation fused with a rectified linear unit operation. The circuitry is configured to detect a negative output of the operation before completion of the operation, clock gate a portion of the circuitry, and output a zero value for the rectified linear unit operation.

Abstract: An apparatus to facilitate distinct paths counterexamples and stimuli generation is disclosed. The apparatus includes processing circuitry to: generate a graph representation structure from a data flow of a hardware design; for each leaf node of the graph representation structure, generate a cover property that is to provide a set of space constraints of the graph representation structure and to query whether a verification property is satisfied by the hardware design having the set of space constraints applied, wherein the set of space constraints define a path through the graph representation structure from a root node to the leaf node; execute, as a single run of a verification tool, a set of cover properties comprising the cover property for each of the leaf nodes; and report results of execution of the set of cover properties as a set of counterexamples for the hardware design.

Abstract: Examples relate to an apparatus, a device, a method, and a computer program for generating a register transfer level (RTL) representation of a circuit. The apparatus comprises processing circuitry configured to generate a graph representation of the circuit, the graph representation comprising a first set of vertices representing operators and a second set of vertices representing operands of the RTL representation of the circuit. The processing circuitry is configured to determine, for one or more operators represented by the one or more vertices of the first set of vertices of the graph, one or more logically equivalent operators. The processing circuitry is configured to include the one or more logically equivalent operators in the graph representation, such that the graph representation comprises a plurality of logically equivalent representations of the circuit.

Abstract: Described herein is a technique for automatic generation of optimized RTL via redundant code removal. By automatically introducing local mutations into the original RTL and using equivalence checking tools to confirm that the functionality it is not affected, optimized RTL can be produced automatically without requiring human intervention.

Abstract: Described herein are techniques for automatic bug fixing of implementation RTL code to transform the code into RTL code that is closer to a reference specification. Two designs, such as a known-good reference specification and an updated implementation, can be compared in functionality via an e-graph. Rewrites are applied from the direction of the specification code to find a design that is equivalent to the specification, but syntactically close to the current implementation.

Abstract: An apparatus to facilitate level-of-detail (LoD) eigenvector determination in a graphics environment is disclosed. The apparatus includes a processing core comprising a rasterizer hardware unit to: identify components of partial derivative vectors corresponding to two adjacent lines of a quadrilateral in texture space of an image, the quadrilateral corresponding to a pixel sampling area in screen space; combine the partial derivative vectors into a transformation matrix representing a transformation of coordinates from the screen space to the texture space; determine a value of a square of a major axis length (major squared) of the ellipse based on a sum of squares (SOS) of the components of the transformation matrix and a determinant of the transformation matrix; and compute eigenvector values for the ellipse using the components of the partial derivative vectors, the determinant of the transformation matrix, and the value of the major squared.

Abstract: An apparatus to facilitate level-of-detail (LoD) determination using major squared and efficient clamping in a graphics environment is disclosed. The apparatus includes a processing core comprising a rasterizer hardware unit to: identify components of partial derivative vectors corresponding to two adjacent lines of a quadrilateral in texture space of an image, the quadrilateral corresponding to a pixel sampling area in screen space; combine the partial derivative vectors into a transformation matrix representing a transformation of coordinates from the screen space to the texture space; determine a value of a square of a major axis length (major squared) of the ellipse based on a sum of squares (SOS) of the components of the transformation matrix and a determinant of the transformation matrix; and compute a LoD value and an anisotropic ratio (iratio) value using the determinant of the transformation matrix and the value of the major squared.

Abstract: Systems and methods related to performing arithmetic operations on floating-point numbers. Floating-point arithmetic circuitry is configured to receive two floating-point numbers. The floating-point arithmetic circuitry includes a first path configured to perform a first operation on the two floating-point numbers based at least in part on a difference in size between the two floating-point numbers. The floating-point arithmetic circuitry includes a second path configured to perform a second operation on the two floating-point numbers based at least in part on the difference is size between the two floating-point numbers. The first path and the second path diverge from each other after receipt of the floating-point numbers in the floating-point arithmetic circuitry and converge on a shared adder that is used for the first operation and the second operation.

Abstract: A device, method, and non-transitory computer-readable medium for generating one or more equivalent designs between a first and second circuit designs. Graphs for the first and second design are created each consisting of vertices representing operators and operands, with edges representing relationships between them. These graphs are combined into a third graph that is modified to include multiple logically equivalent designs to the original two designs by determining equivalent operators for certain vertices. From the logically equivalent designs in the third graph, a set of shared designs is extracted, consisting of vertices that are common between the equivalent designs in the first and second graphs. These shared designs may be expressed in a register transfer level (RTL) representation for validation and equivalence checking.

Abstract: An example relates to an apparatus for generating a register transfer level (RTL) representation of a circuit, the apparatus comprising interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions to generate a graph representation of the circuit, the graph representation comprising a first set of vertices representing operators and a second set of vertices representing operands of the graph representation of the circuit. The processing circuitry is to execute the machine-readable instructions to identify one or more conditional operators, with each conditional operator defining at least two possible outcomes depending on the condition, and with each possible outcome being represented by a branch of the graph representation of the circuit. The processing circuitry is to execute the machine-readable instructions to determine, for the possible outcomes of the one or more conditional operators, a condition imposed by the respective outcome.

Abstract: Described herein is a truncated modified Booth squarer that is commutative and accurate to 1 unit in the last place. In various embodiments, the truncated Booth squarer is a radix-4 Booth squarer or a radix-8 Booth squarer. The truncated Booth squarer can be included within integer, floating-point, or fixed-point units within a graphics processor or compute accelerator, including matrix accelerator units or tensor processors.