Abstract: Described herein are techniques for automatic bug fixing of implementation RTL code to transform the code into RTL code that is closer to a reference specification. Two designs, such as a known-good reference specification and an updated implementation, can be compared in functionality via an e-graph. Rewrites are applied from the direction of the specification code to find a design that is equivalent to the specification, but syntactically close to the current implementation.

Abstract: An apparatus to facilitate level-of-detail (LoD) eigenvector determination in a graphics environment is disclosed. The apparatus includes a processing core comprising a rasterizer hardware unit to: identify components of partial derivative vectors corresponding to two adjacent lines of a quadrilateral in texture space of an image, the quadrilateral corresponding to a pixel sampling area in screen space; combine the partial derivative vectors into a transformation matrix representing a transformation of coordinates from the screen space to the texture space; determine a value of a square of a major axis length (major squared) of the ellipse based on a sum of squares (SOS) of the components of the transformation matrix and a determinant of the transformation matrix; and compute eigenvector values for the ellipse using the components of the partial derivative vectors, the determinant of the transformation matrix, and the value of the major squared.

Abstract: An apparatus to facilitate level-of-detail (LoD) determination using major squared and efficient clamping in a graphics environment is disclosed. The apparatus includes a processing core comprising a rasterizer hardware unit to: identify components of partial derivative vectors corresponding to two adjacent lines of a quadrilateral in texture space of an image, the quadrilateral corresponding to a pixel sampling area in screen space; combine the partial derivative vectors into a transformation matrix representing a transformation of coordinates from the screen space to the texture space; determine a value of a square of a major axis length (major squared) of the ellipse based on a sum of squares (SOS) of the components of the transformation matrix and a determinant of the transformation matrix; and compute a LoD value and an anisotropic ratio (iratio) value using the determinant of the transformation matrix and the value of the major squared.

Abstract: Systems and methods related to performing arithmetic operations on floating-point numbers. Floating-point arithmetic circuitry is configured to receive two floating-point numbers. The floating-point arithmetic circuitry includes a first path configured to perform a first operation on the two floating-point numbers based at least in part on a difference in size between the two floating-point numbers. The floating-point arithmetic circuitry includes a second path configured to perform a second operation on the two floating-point numbers based at least in part on the difference is size between the two floating-point numbers. The first path and the second path diverge from each other after receipt of the floating-point numbers in the floating-point arithmetic circuitry and converge on a shared adder that is used for the first operation and the second operation.

Abstract: A device, method, and non-transitory computer-readable medium for generating one or more equivalent designs between a first and second circuit designs. Graphs for the first and second design are created each consisting of vertices representing operators and operands, with edges representing relationships between them. These graphs are combined into a third graph that is modified to include multiple logically equivalent designs to the original two designs by determining equivalent operators for certain vertices. From the logically equivalent designs in the third graph, a set of shared designs is extracted, consisting of vertices that are common between the equivalent designs in the first and second graphs. These shared designs may be expressed in a register transfer level (RTL) representation for validation and equivalence checking.

Abstract: An example relates to an apparatus for generating a register transfer level (RTL) representation of a circuit, the apparatus comprising interface circuitry, machine-readable instructions and processing circuitry to execute the machine-readable instructions to generate a graph representation of the circuit, the graph representation comprising a first set of vertices representing operators and a second set of vertices representing operands of the graph representation of the circuit. The processing circuitry is to execute the machine-readable instructions to identify one or more conditional operators, with each conditional operator defining at least two possible outcomes depending on the condition, and with each possible outcome being represented by a branch of the graph representation of the circuit. The processing circuitry is to execute the machine-readable instructions to determine, for the possible outcomes of the one or more conditional operators, a condition imposed by the respective outcome.

Abstract: Computer computation of correctly rounded floating point summation is described. An example of apparatus includes a first circuit to sort multiple floating point (FP) values based on an exponent of each FP value and store the sorted FP values in a buffer, and to provide the plurality of FP values for summation sequentially in a sorted order starting with a FP value having a smallest exponent; a second circuit to iteratively sum the FP values and store an accumulated value, generate and store a residual value representing fully resolved bits from the accumulator, and generate an intermediate output including the residual value; and a third circuit to perform final rounding of the output, the final rounded output being a correctly rounded summation of the maximum floating point values.

Abstract: Described herein is a truncated modified Booth squarer that is commutative and accurate to 1 unit in the last place. In various embodiments, the truncated Booth squarer is a radix-4 Booth squarer or a radix-8 Booth squarer. The truncated Booth squarer can be included within integer, floating-point, or fixed-point units within a graphics processor or compute accelerator, including matrix accelerator units or tensor processors.

Abstract: Computer computation of exact floating point addition is described. An example of an apparatus includes a first circuit to add first and second floating point inputs, including sorting the inputs to identify a larger input and a smaller input, adding bits in an upper portion of the smaller input to bits of the larger input, generating a high intermediate value based on the sum, and a generating a low intermediate value based on a lower portion of the lower input; and a second circuit to generate first and second outputs based on the high and low intermediate values, wherein the first output plus the second output exactly equals the first input plus the second input.

Abstract: Described herein is a technique to implement an efficient floating-point n-input sum of squares operation using faithful rounding to 1 unit in the place (ULP) instead of IEEE rounding. The resulting circuitry is useful to accelerate graphics algorithms that don't require fully IEEE compliant hardware. Multipliers that are 1ulp can be significantly smaller, faster and more power efficient than IEEE rounded multipliers.

Abstract: Described herein is a generalized optimal reduction scheme for reducing an array modulo a constant. The constant modulo operation calculates a result for array of bits xi, width n modulo an odd positive integer constant d, (e.g., x[n:0] mod d). Circuitry to perform such operation can be configured to compress the array of bits xi, width n into an array of bits yi width m. The techniques described herein enable the design of optimal circuitry via iterative exploration of all potential reduction strategies that are available given the input constraints.

Abstract: The techniques described in the detailed description above enable the manufacturing of circuits with increased performance and efficiency when performing division by a constant number. One embodiment provides circuitry including an input circuit to receive an input value including a plurality of bits, a logarithmic tree coupled with the input circuit, the logarithmic tree configured to compute an array of values based on a plurality of multi-bit groups of the plurality of bits of the input value, each value in the array of values includes a modulus of a corresponding multi-bit group with respect to the constant, a binary array adder to compute a quotient of the division operation based on the array of values, the input value, and the constant, and an output circuit to output the quotient.

Abstract: Described herein is a technique for automatic program code optimization for high-level synthesis. One embodiment provides a method comprising receiving input including first program code in a high-level language; translating the first program code into an intermediate language; constructing an equality graph (e-graph) from the intermediate language; interleaving control-flow, data path, and gate-level transformations to explore equivalent hardware designs represented by the e-graph; selecting a hardware design based on a cost function; extracting a representation of a selected hardware design in the intermediate language; generating second program code in the high-level language; and performing high-level synthesis using the second program code.

Abstract: Embodiments provided a blend circuit configured to perform a power optimized blend using blend circuitry configured such that the dynamic power consumed during the blending of two input color values is reduced when the input colors are close in value. When blending two identical input color values, a portion of the blend circuit can be bypassed and clock and/or data gated.

Abstract: Described herein are techniques to automatically create a software model which covers the core functionality of a semiconductor design to be formally verified and can be easily consumed by a formal verification tool for software or semiconductor designs. These techniques enable verification engineers to expand the scope of formal verification to fix both software and RTL bugs, saving significant design time and reducing the time to market of for new products.

Abstract: Described herein is a technique and associated tool for automatic program code optimization for high-level synthesis. The tool can efficiently explore multiple representations of an input program using e-graph rewriting and determine an HLS-efficient representation of program code for input into high-level synthesis tools.

Abstract: Described herein is a technique for automated detection of case-splitting opportunities in RTL. The techniques described herein facilitate the integration of case-splitting into a hardware design tool flow, allowing the generation of hardware designs that do not suffer from timing violations. One embodiment provides a method comprising analyzing a first hardware description in a hardware description language to identify a critical path in a circuit represented by the hardware description, automatically detecting a case-splitting opportunity within the critical path, generating hardware description language for a case split having determined operator domain restrictions, and outputting a second hardware description including the hardware description language for the case split, wherein the second hardware description has a reduced operator hardware cost for the critical path relative to the first hardware description.

Abstract: An apparatus to facilitate hardware enhancements for double precision systolic support is disclosed. The apparatus includes matrix acceleration hardware having double-precision (DP) matrix multiplication circuitry including a multiplier circuits to multiply pairs of input source operands in a DP floating-point format; adders to receive multiplier outputs from the multiplier circuits and accumulate the multiplier outputs in a high precision intermediate format; an accumulator circuit to accumulate adder outputs from the adders with at least one of a third global source operand on a first pass of the DP matrix multiplication circuitry or an intermediate result from the first pass on a second pass of the DP matrix multiplication circuitry, wherein the accumulator circuit to generate an accumulator output in the high precision intermediate format; and a down conversion and rounding circuit to down convert and round an output of the second pass as final result in the DP floating-point format.

Abstract: Described herein is a technique to enable the construction of hierarchical clock gating architectures via e-graph rewriting. Automated clock gating relies on multiplexor (mux) tree analysis and constructs simple register enable signals. A framework is provided to detect non-mux based opportunities and construct more complex clock gating signals.

Abstract: Described herein are techniques for automated hardware power optimization via e-graph based automatic RTL exploration. These techniques provide a tool that automatically performs RTL optimization and generates power optimized RTL without requiring design engineers to perform labor and knowledge intensive manual optimizations.