Patents by Inventor Theo Standaert
Theo Standaert has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 11404311Abstract: Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.Type: GrantFiled: January 15, 2020Date of Patent: August 2, 2022Assignee: International Business Machines CorporationInventors: Cornelius Brown Peethala, Kedari Matam, Chih-Chao Yang, Theo Standaert
-
Patent number: 11315830Abstract: Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.Type: GrantFiled: January 15, 2020Date of Patent: April 26, 2022Assignee: International Business Machines CorporationInventors: Cornelius Brown Peethala, Kedari Matam, Chih-Chao Yang, Theo Standaert
-
Publication number: 20210091010Abstract: Back-end-of-the line (BEOL) interconnect structures are provided in which an alternative metal such as, for example, a noble metal, is present in a combined via/line opening that is formed in an interconnect dielectric material layer. A surface diffusion dominated reflow anneal is used to reduce the thickness of a noble metal layer outside the combined via/line opening thus reducing or eliminating the burden of polishing the noble metal layer. In some embodiments and after performing the anneal, a lesser noble metal layer can be formed atop the noble metal layer prior to polishing. The use of the lesser noble metal layer may further reduce the burden of polishing the noble metal layer.Type: ApplicationFiled: December 8, 2020Publication date: March 25, 2021Inventors: Chih-Chao Yang, Theo Standaert
-
Patent number: 10886225Abstract: Back-end-of-the line (BEOL) interconnect structures are provided in which an alternative metal such as, for example, a noble metal, is present in a combined via/line opening that is formed in an interconnect dielectric material layer. A surface diffusion dominated reflow anneal is used to reduce the thickness of a noble metal layer outside the combined via/line opening thus reducing or eliminating the burden of polishing the noble metal layer. In some embodiments and after performing the anneal, a lesser noble metal layer can be formed atop the noble metal layer prior to polishing. The use of the lesser noble metal layer may further reduce the burden of polishing the noble metal layer.Type: GrantFiled: March 5, 2018Date of Patent: January 5, 2021Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Theo Standaert
-
Patent number: 10672649Abstract: Advanced dual damascene interconnects have been provided in which a metallic seed liner composed of an electrically conductive metal or metal alloy having a first bulk resistivity is located on sidewall surfaces and a bottom wall of a first metallic structure that is present in a via portion of a combined via/line opening that is present in an interconnect dielectric material layer. The first metallic structure is composed of an electrically conductive metal or metal alloy that has a second bulk resistivity that is higher than the first bulk resistivity. In some embodiments, a second metal structure is present on a topmost surface of the first metallic structure. The second metallic structure is composed of an electrically conductive metal or metal alloy that differs from the electrically conductive metal or metal alloy of the first metallic structure.Type: GrantFiled: November 8, 2017Date of Patent: June 2, 2020Assignee: International Business Machines CorporationInventors: Chih-Chao Yang, Theo Standaert
-
Patent number: 10672653Abstract: Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.Type: GrantFiled: December 18, 2017Date of Patent: June 2, 2020Assignee: International Business Machines CorporationInventors: Cornelius Brown Peethala, Kedari Matam, Chih-Chao Yang, Theo Standaert
-
Publication number: 20200152511Abstract: Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Cornelius Brown Peethala, Kedari Matam, Chih-Chao Yang, Theo Standaert
-
Publication number: 20200152510Abstract: Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.Type: ApplicationFiled: January 15, 2020Publication date: May 14, 2020Inventors: Cornelius Brown Peethala, Kedari Matam, Chih-Chao Yang, Theo Standaert
-
Patent number: 10534888Abstract: A computer implemented method, a system and a computer readable storage medium configured to conduct the following: determining a reliability parameter of an initial hybrid metallization to determine a determined reliability parameter, comparing the determined reliability parameter to a reliability limit and determining a reliability ratio, determining a performance parameter of the initial hybrid metallization to determine a determined performance parameter, comparing the determined performance parameter to a performance limit and determining a performance ratio, determining a reliability indice from the reliability ratio, determining a performance indice from the performance ratio, determining a reliability score from a combination of the determined reliability parameter and the reliability indice, determining a performance score from a combination of the determined performance parameter and the performance indice, comparing the reliability score to the performance score, selecting a first interconnect andType: GrantFiled: January 3, 2018Date of Patent: January 14, 2020Assignee: International Business Machines CorporationInventors: Baozhen Li, Chih-Chao Yang, Theo Standaert
-
Publication number: 20190273047Abstract: Back-end-of-the line (BEOL) interconnect structures are provided in which an alternative metal such as, for example, a noble metal, is present in a combined via/line opening that is formed in an interconnect dielectric material layer. A surface diffusion dominated reflow anneal is used to reduce the thickness of a noble metal layer outside the combined via/line opening thus reducing or eliminating the burden of polishing the noble metal layer. In some embodiments and after performing the anneal, a lesser noble metal layer can be formed atop the noble metal layer prior to polishing. The use of the lesser noble metal layer may further reduce the burden of polishing the noble metal layer.Type: ApplicationFiled: March 5, 2018Publication date: September 5, 2019Inventors: Chih-Chao Yang, Theo Standaert
-
Publication number: 20190205496Abstract: A computer implemented method, a system and a computer readable storage medium configured to conduct the following: determining a reliability parameter of an initial hybrid metallization to determine a determined reliability parameter, comparing the determined reliability parameter to a reliability limit and determining a reliability ratio, determining a performance parameter of the initial hybrid metallization to determine a determined performance parameter, comparing the determined performance parameter to a performance limit and determining a performance ratio, determining a reliability indice from the reliability ratio, determining a performance indice from the performance ratio, determining a reliability score from a combination of the determined reliability parameter and the reliability indice, determining a performance score from a combination of the determined performance parameter and the performance indice, comparing the reliability score to the performance score, selecting a first interconnect andType: ApplicationFiled: January 3, 2018Publication date: July 4, 2019Inventors: Baozhen Li, Chih-Chao Yang, Theo Standaert
-
Publication number: 20190189508Abstract: Techniques are provided to fabricate metal interconnects using liner planarization-free process flows. A sacrificial layer is formed on a dielectric layer, and the sacrificial and dielectric layers are patterned to form an opening in the dielectric layer. A conformal liner layer is deposited, and a metal layer deposited to form a metal interconnect in the opening. An overburden portion of the metal layer is planarized to expose an overburden portion of the liner layer. A first wet etch is performed to selectively remove the overburden portion of the liner layer. A second wet etch process is performed to selectively remove the sacrificial layer, resulting in extended portions of the liner layer and the metal interconnect extending above a surface of the dielectric layer. A dielectric capping layer is formed to cover the sidewall and upper surfaces of the extended portions of the liner layer and the metal interconnect.Type: ApplicationFiled: December 18, 2017Publication date: June 20, 2019Inventors: Cornelius Brown Peethala, Kedari Matam, Chih-Chao Yang, Theo Standaert
-
Publication number: 20190139821Abstract: Advanced dual damascene interconnects that exhibit controlled via resistance and, in some instances, controlled line resistance are provided. In one embodiment, the structure includes an interconnect level having a combined via/line opening located therein. A diffusion barrier liner is located in at least the via portion of the combined via/line opening. A first metallic structure composed of an electrically conductive metal or metal alloy having a first bulk resistivity is located in at least the via portion of the combined via/line opening. A second metallic structure composed of an electrically conductive metal or metal alloy that has a second bulk resistivity that is higher than the first bulk resistivity is located in at least the line portion of the combined via/line opening. In accordance with the present application, second metallic structure is in direct contact with the first metallic structure.Type: ApplicationFiled: November 8, 2017Publication date: May 9, 2019Inventors: Chih-Chao Yang, Theo Standaert
-
Publication number: 20190139820Abstract: Advanced dual damascene interconnects have been provided in which a metallic seed liner composed of an electrically conductive metal or metal alloy having a first bulk resistivity is located on sidewall surfaces and a bottom wall of a first metallic structure that is present in a via portion of a combined via/line opening that is present in an interconnect dielectric material layer. The first metallic structure is composed of an electrically conductive metal or metal alloy that has a second bulk resistivity that is higher than the first bulk resistivity. In some embodiments, a second metal structure is present on a topmost surface of the first metallic structure. The second metallic structure is composed of an electrically conductive metal or metal alloy that differs from the electrically conductive metal or metal alloy of the first metallic structure.Type: ApplicationFiled: November 8, 2017Publication date: May 9, 2019Inventors: Chih-Chao Yang, Theo Standaert