Abstract: Circuitry for actively reducing the effects of ground voltage fluctuations in integrated circuits is described. An input buffer circuit including an output transistor 30 is provided along with a compensation circuit that is designed to reference the base of transistor 30 to an internal ground node of the integrated circuit. The compensation circuit includes a control diode 46, compensation transistors 42 and 43, bias resistors 40, 41 and 45 and diode chain 47, 48 and 49. In operation, the compensation circuit prevents the undesirable switching of output transistor 30 under low input voltage conditions by actively coupling the base of transistor 30 to internal ground through two conducting compensation transistors 43 and 42. Under these conditions, control diode 46 remains reverse biased allowing current flow through diode string 47, 48, and 49 which establish a threshold voltage to set the level at which compensation transistor 43 turns on.

Abstract: An input circuit is provided which receives TTL voltage signals as input and transmits CMOS voltage signal levels. A separation transistor connected to a voltage divider network is included within the circuit to separate the two gates of a CMOS inverter from the TTL input such that one gate of the inverter is fully off when the other gate is on and fully on when the other gate is off. Thus internal ground voltage fluctuations during operation of the circuit are avoided.

Abstract: A power-up 3-state circuit implemented with BiCMOS techniques is described. The circuit disables itself and draws no through current once the operating level of the applied supply voltage is achieved.